Lines Matching refs:args
99 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
116 args.ucAction = ATOM_LCD_BLOFF;
117 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
119 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
120 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
121 args.ucAction = ATOM_LCD_BLON;
122 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
358 DAC_ENCODER_CONTROL_PS_ALLOCATION args;
362 memset(&args, 0, sizeof(args));
375 args.ucAction = action;
378 args.ucDacStandard = ATOM_DAC1_PS2;
380 args.ucDacStandard = ATOM_DAC1_CV;
388 args.ucDacStandard = ATOM_DAC1_PAL;
394 args.ucDacStandard = ATOM_DAC1_NTSC;
398 args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
400 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
410 TV_ENCODER_CONTROL_PS_ALLOCATION args;
414 memset(&args, 0, sizeof(args));
418 args.sTVEncoder.ucAction = action;
421 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
425 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
428 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
431 args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
434 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
437 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
440 args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
443 args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
446 args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
449 args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
454 args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
456 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
499 union dvo_encoder_control args;
503 memset(&args, 0, sizeof(args));
517 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
520 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
522 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
526 args.dvo.sDVOEncoder.ucAction = action;
527 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
529 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
532 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
536 args.dvo_v3.ucAction = action;
537 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
538 args.dvo_v3.ucDVOConfig = 0; /* XXX */
542 args.dvo_v4.ucAction = action;
543 args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
544 args.dvo_v4.ucDVOConfig = 0; /* XXX */
545 args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
557 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
572 union lvds_encoder_control args;
583 memset(&args, 0, sizeof(args));
609 args.v1.ucMisc = 0;
610 args.v1.ucAction = action;
612 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
613 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
616 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
618 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
621 args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
623 args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
625 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
630 args.v2.ucMisc = 0;
631 args.v2.ucAction = action;
634 args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
637 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
638 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
639 args.v2.ucTruncate = 0;
640 args.v2.ucSpatial = 0;
641 args.v2.ucTemporal = 0;
642 args.v2.ucFRC = 0;
645 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
647 args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
649 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
652 args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
654 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
656 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
660 args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
662 args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
675 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
854 union dig_encoder_control args;
875 memset(&args, 0, sizeof(args));
893 args.v1.ucAction = action;
894 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
896 args.v3.ucPanelMode = panel_mode;
898 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
900 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
901 args.v1.ucLaneNum = dp_lane_count;
903 args.v1.ucLaneNum = 8;
905 args.v1.ucLaneNum = 4;
909 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
913 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
916 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
920 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
922 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
924 if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
925 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
930 args.v3.ucAction = action;
931 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
933 args.v3.ucPanelMode = panel_mode;
935 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
937 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
938 args.v3.ucLaneNum = dp_lane_count;
940 args.v3.ucLaneNum = 8;
942 args.v3.ucLaneNum = 4;
944 if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
945 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
947 args.v3.acConfig.ucDigSel = enc_override;
949 args.v3.acConfig.ucDigSel = dig->dig_encoder;
950 args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
953 args.v4.ucAction = action;
954 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
956 args.v4.ucPanelMode = panel_mode;
958 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
960 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
961 args.v4.ucLaneNum = dp_lane_count;
963 args.v4.ucLaneNum = 8;
965 args.v4.ucLaneNum = 4;
967 if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
969 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
971 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
973 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
975 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
979 args.v4.acConfig.ucDigSel = enc_override;
981 args.v4.acConfig.ucDigSel = dig->dig_encoder;
982 args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
984 args.v4.ucHPD_ID = 0;
986 args.v4.ucHPD_ID = hpd_id + 1;
998 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1024 union dig_transmitter_control args;
1070 memset(&args, 0, sizeof(args));
1094 args.v1.ucAction = action;
1096 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1098 args.v1.asMode.ucLaneSel = lane_num;
1099 args.v1.asMode.ucLaneSet = lane_set;
1102 args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1104 args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1106 args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1109 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1112 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1114 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1121 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1123 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1125 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1127 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1130 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1132 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1137 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1139 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1142 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1145 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1147 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1151 args.v2.ucAction = action;
1153 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1155 args.v2.asMode.ucLaneSel = lane_num;
1156 args.v2.asMode.ucLaneSet = lane_set;
1159 args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1161 args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1163 args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1166 args.v2.acConfig.ucEncoderSel = dig_encoder;
1168 args.v2.acConfig.ucLinkSel = 1;
1172 args.v2.acConfig.ucTransmitterSel = 0;
1175 args.v2.acConfig.ucTransmitterSel = 1;
1178 args.v2.acConfig.ucTransmitterSel = 2;
1183 args.v2.acConfig.fCoherentMode = 1;
1184 args.v2.acConfig.fDPConnector = 1;
1187 args.v2.acConfig.fCoherentMode = 1;
1189 args.v2.acConfig.fDualLinkConnector = 1;
1193 args.v3.ucAction = action;
1195 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1197 args.v3.asMode.ucLaneSel = lane_num;
1198 args.v3.asMode.ucLaneSet = lane_set;
1201 args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1203 args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1205 args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1209 args.v3.ucLaneNum = dp_lane_count;
1211 args.v3.ucLaneNum = 8;
1213 args.v3.ucLaneNum = 4;
1216 args.v3.acConfig.ucLinkSel = 1;
1218 args.v3.acConfig.ucEncoderSel = 1;
1226 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1228 args.v3.acConfig.ucRefClkSource = pll_id;
1232 args.v3.acConfig.ucTransmitterSel = 0;
1235 args.v3.acConfig.ucTransmitterSel = 1;
1238 args.v3.acConfig.ucTransmitterSel = 2;
1243 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1246 args.v3.acConfig.fCoherentMode = 1;
1248 args.v3.acConfig.fDualLinkConnector = 1;
1252 args.v4.ucAction = action;
1254 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1256 args.v4.asMode.ucLaneSel = lane_num;
1257 args.v4.asMode.ucLaneSet = lane_set;
1260 args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1262 args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1264 args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1268 args.v4.ucLaneNum = dp_lane_count;
1270 args.v4.ucLaneNum = 8;
1272 args.v4.ucLaneNum = 4;
1275 args.v4.acConfig.ucLinkSel = 1;
1277 args.v4.acConfig.ucEncoderSel = 1;
1286 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1288 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1290 args.v4.acConfig.ucRefClkSource = pll_id;
1294 args.v4.acConfig.ucTransmitterSel = 0;
1297 args.v4.acConfig.ucTransmitterSel = 1;
1300 args.v4.acConfig.ucTransmitterSel = 2;
1305 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1308 args.v4.acConfig.fCoherentMode = 1;
1310 args.v4.acConfig.fDualLinkConnector = 1;
1314 args.v5.ucAction = action;
1316 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1318 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1323 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1325 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1329 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1331 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1335 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1337 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1340 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1344 args.v5.ucLaneNum = dp_lane_count;
1346 args.v5.ucLaneNum = 8;
1348 args.v5.ucLaneNum = 4;
1349 args.v5.ucConnObjId = connector_object_id;
1350 args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1353 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1355 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1358 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1361 args.v5.asConfig.ucCoherentMode = 1;
1364 args.v5.asConfig.ucHPDSel = 0;
1366 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1367 args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1368 args.v5.ucDPLaneSet = lane_set;
1380 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1395 union dig_transmitter_control args;
1412 memset(&args, 0, sizeof(args));
1414 args.v1.ucAction = action;
1416 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1447 union external_encoder_control args;
1472 memset(&args, 0, sizeof(args));
1485 args.v1.sDigEncoder.ucAction = action;
1486 args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1487 args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1489 if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1491 args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1492 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1494 args.v1.sDigEncoder.ucLaneNum = 8;
1496 args.v1.sDigEncoder.ucLaneNum = 4;
1499 args.v3.sExtEncoder.ucAction = action;
1501 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1503 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1504 args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1506 if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1508 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1510 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1511 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1513 args.v3.sExtEncoder.ucLaneNum = 8;
1515 args.v3.sExtEncoder.ucLaneNum = 4;
1518 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1521 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1524 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1527 args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1538 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1548 ENABLE_YUV_PS_ALLOCATION args;
1552 memset(&args, 0, sizeof(args));
1570 args.ucEnable = ATOM_ENABLE;
1571 args.ucCRTC = radeon_crtc->crtc_id;
1573 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1584 DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1587 memset(&args, 0, sizeof(args));
1632 args.ucAction = ATOM_ENABLE;
1637 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1640 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1647 args.ucAction = ATOM_LCD_BLON;
1648 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1655 args.ucAction = ATOM_DISABLE;
1656 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1658 args.ucAction = ATOM_LCD_BLOFF;
1659 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1871 union crtc_source_param args;
1876 memset(&args, 0, sizeof(args));
1887 args.v1.ucCRTC = radeon_crtc->crtc_id;
1890 args.v1.ucCRTC = radeon_crtc->crtc_id;
1892 args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1897 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1902 args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1904 args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1909 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1914 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1916 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1918 args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1923 args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1925 args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1927 args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1932 args.v2.ucCRTC = radeon_crtc->crtc_id;
1937 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1939 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1941 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1943 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1945 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1956 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1959 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1962 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1965 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1968 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1971 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1974 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1979 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1983 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1985 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1987 args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1991 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1993 args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1995 args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
2006 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2020 union crtc_source_param args;
2022 memset(&args, 0, sizeof(args));
2030 args.v2.ucCRTC = radeon_crtc->crtc_id;
2031 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2035 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2038 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2041 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2044 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2047 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2050 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2053 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2056 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2350 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2354 memset(&args, 0, sizeof(args));
2359 args.sDacload.ucMisc = 0;
2363 args.sDacload.ucDacType = ATOM_DAC_A;
2365 args.sDacload.ucDacType = ATOM_DAC_B;
2368 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2370 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2372 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2374 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2376 args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2378 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2381 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);