Lines Matching defs:clock
566 u32 adjusted_clock = mode->clock;
568 u32 dp_clock = mode->clock;
569 u32 clock = mode->clock;
571 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
583 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
597 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
602 if (mode->clock > 200000) /* range limits??? */
641 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
643 adjusted_clock = mode->clock * 2;
662 clock = (clock * 5) / 4;
665 clock = (clock * 3) / 2;
668 clock = clock * 2;
673 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
694 args.v1.usPixelClock = cpu_to_le16(clock / 10);
706 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
791 /* if the default dcpll clock is specified,
799 /* if the default dcpll clock is specified,
827 u32 clock,
852 if (clock == ATOM_DISABLE)
854 args.v1.usPixelClock = cpu_to_le16(clock / 10);
864 args.v2.usPixelClock = cpu_to_le16(clock / 10);
874 args.v3.usPixelClock = cpu_to_le16(clock / 10);
891 args.v5.usPixelClock = cpu_to_le16(clock / 10);
920 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
987 /* Assign mode clock for hdmi deep color max clock limit check */
988 radeon_connector->pixelclock_for_modeset = mode->clock;
1028 mode->clock / 10);
1041 mode->clock / 10);
1049 mode->clock / 10);
1056 /* adjust pixel clock as needed */
1069 u32 pll_clock = mode->clock;
1070 u32 clock = mode->clock;
1075 /* pass the actual clock to atombios_crtc_program_pll for DCE5,6 for HDMI */
1079 clock = radeon_crtc->adjusted_clock;
1083 pll = &rdev->clock.p1pll;
1086 pll = &rdev->clock.p2pll;
1091 pll = &rdev->clock.dcpll;
1115 encoder_mode, radeon_encoder->encoder_id, clock,
1793 * be shared (i.e., same clock).
1825 /* for non-DP check the clock */
1827 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1886 if (rdev->clock.dp_extclk)
1887 /* skip PPLL programming if using ext clock */
1896 /* use the same PPLL for all monitors with the same clock */
1934 if (rdev->clock.dp_extclk)
1935 /* skip PPLL programming if using ext clock */
1944 /* use the same PPLL for all monitors with the same clock */
1960 if (rdev->clock.dp_extclk)
1961 /* skip PPLL programming if using ext clock */
1972 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1974 * DCE4: PPLL or ext clock
1975 * DCE5: PPLL, DCPLL, or ext clock
1976 * DCE6: PPLL, PPLL0, or ext clock
1980 * crtc virtual pixel clock.
1983 if (rdev->clock.dp_extclk)
1984 /* skip PPLL programming if using ext clock */
1999 /* use the same PPLL for all monitors with the same clock */
2023 * both use same clock.
2036 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2041 rdev->clock.default_dispclk);
2045 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);