Lines Matching refs:ret
98 int ret;
103 ret = spi_write(spi, (u8 *)&tx_buf, sizeof(tx_buf));
104 if (ret < 0) {
105 dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
107 *err = ret;
110 return ret;
119 int ret;
127 ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
128 if (ret < 0) {
129 dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
131 *err = ret;
134 return ret;
143 int ret;
152 ret = spi_write(spi, (u8 *)tx_buf, sizeof(tx_buf));
153 if (ret < 0) {
154 dev_err(&spi->dev, "%s: SPI write failed: %d\n", __func__, ret);
156 *err = ret;
159 return ret;
166 int ret = 0;
170 jbt_ret_write_0(lcd, 0x00, &ret);
175 jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x17, &ret);
178 jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE, 0x80, &ret);
181 jbt_reg_write_1(lcd, JBT_REG_QUAD_RATE, 0x00, &ret);
184 jbt_reg_write_1(lcd, JBT_REG_POWER_ON_OFF, 0x16, &ret);
187 jbt_reg_write_2(lcd, JBT_REG_OUTPUT_CONTROL, 0xfff9, &ret);
190 jbt_ret_write_0(lcd, JBT_REG_SLEEP_OUT, &ret);
195 jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE1, 0x01, &ret);
196 jbt_reg_write_1(lcd, JBT_REG_DISPLAY_MODE2, 0x00, &ret);
197 jbt_reg_write_1(lcd, JBT_REG_RGB_FORMAT, 0x60, &ret);
198 jbt_reg_write_1(lcd, JBT_REG_DRIVE_SYSTEM, 0x10, &ret);
199 jbt_reg_write_1(lcd, JBT_REG_BOOSTER_OP, 0x56, &ret);
200 jbt_reg_write_1(lcd, JBT_REG_BOOSTER_MODE, 0x33, &ret);
201 jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
202 jbt_reg_write_1(lcd, JBT_REG_BOOSTER_FREQ, 0x11, &ret);
203 jbt_reg_write_1(lcd, JBT_REG_OPAMP_SYSCLK, 0x02, &ret);
204 jbt_reg_write_1(lcd, JBT_REG_VSC_VOLTAGE, 0x2b, &ret);
205 jbt_reg_write_1(lcd, JBT_REG_VCOM_VOLTAGE, 0x40, &ret);
206 jbt_reg_write_1(lcd, JBT_REG_EXT_DISPL, 0x03, &ret);
207 jbt_reg_write_1(lcd, JBT_REG_DCCLK_DCEV, 0x04, &ret);
212 jbt_reg_write_1(lcd, JBT_REG_ASW_SLEW, 0x04, &ret);
213 jbt_reg_write_1(lcd, JBT_REG_DUMMY_DISPLAY, 0x00, &ret);
215 jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_A, 0x11, &ret);
216 jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_B, 0x11, &ret);
217 jbt_reg_write_1(lcd, JBT_REG_SLEEP_OUT_FR_C, 0x11, &ret);
218 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040, &ret);
219 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0, &ret);
220 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020, &ret);
221 jbt_reg_write_2(lcd, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0, &ret);
223 jbt_reg_write_2(lcd, JBT_REG_GAMMA1_FINE_1, 0x5533, &ret);
224 jbt_reg_write_1(lcd, JBT_REG_GAMMA1_FINE_2, 0x00, &ret);
225 jbt_reg_write_1(lcd, JBT_REG_GAMMA1_INCLINATION, 0x00, &ret);
226 jbt_reg_write_1(lcd, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00, &ret);
228 jbt_reg_write_2(lcd, JBT_REG_HCLOCK_VGA, 0x1f0, &ret);
229 jbt_reg_write_1(lcd, JBT_REG_BLANK_CONTROL, 0x02, &ret);
230 jbt_reg_write_2(lcd, JBT_REG_BLANK_TH_TV, 0x0804, &ret);
232 jbt_reg_write_1(lcd, JBT_REG_CKV_ON_OFF, 0x01, &ret);
233 jbt_reg_write_2(lcd, JBT_REG_CKV_1_2, 0x0000, &ret);
235 jbt_reg_write_2(lcd, JBT_REG_OEV_TIMING, 0x0d0e, &ret);
236 jbt_reg_write_2(lcd, JBT_REG_ASW_TIMING_1, 0x11a4, &ret);
237 jbt_reg_write_1(lcd, JBT_REG_ASW_TIMING_2, 0x0e, &ret);
239 return ret;
245 int ret;
247 ret = jbt_ret_write_0(lcd, JBT_REG_DISPLAY_ON, NULL);
248 if (ret)
249 return ret;
328 int ret;
340 ret = spi_setup(spi);
341 if (ret < 0) {
342 dev_err(&spi->dev, "failed to setup SPI: %d\n", ret);
343 return ret;
349 ret = drm_panel_of_backlight(&lcd->panel);
350 if (ret)
351 return ret;