Lines Matching refs:fck
602 unsigned long fck;
615 fck = pck * pckd;
617 fck = clk_round_rate(dss->dss_clk, fck);
619 return func(fck, data);
633 fck = DIV_ROUND_UP(prate, fckd) * m;
635 if (func(fck, data))
646 DSSDBG("set fck to %lu\n", rate);
673 unsigned long fck;
680 fck = clk_round_rate(dss->dss_clk, max_dss_fck);
686 fck = DIV_ROUND_UP(prate, fck_div)
690 r = dss_set_fck_rate(dss, fck);
824 clk = devm_clk_get(&dss->pdev->dev, "fck");
826 DSSERR("can't get clock fck\n");
1055 * fck div max is really 16, but the divider range has gaps. The range