Lines Matching defs:data
325 const struct dsi_of_data *data;
483 static void dsi_completion_handler(void *data, u32 mask)
485 complete((struct completion *)data);
1139 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC) {
1236 unsigned int lpdiv_max = dsi->data->max_pll_lpdiv;
1286 if ((dsi->data->quirks & DSI_QUIRK_PLL_PWR_BUG) &&
1312 max_dsi_fck = dsi->data->max_fck_freq;
1661 if (!(dsi->data->quirks & DSI_QUIRK_GNQ))
1813 if (dsi->data->quirks & DSI_QUIRK_PHY_DCC) {
1884 if (dsi->data->quirks & DSI_QUIRK_REVERSE_TXCLKESC)
1999 if (dsi->data->model == DSI_MODEL_OMAP4)
2001 if (dsi->data->model == DSI_MODEL_OMAP5)
2008 if (dsi->data->model == DSI_MODEL_OMAP4)
2010 else if (dsi->data->model == DSI_MODEL_OMAP5)
2230 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2233 (struct dsi_packet_sent_handler_data *) data;
2280 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2283 (struct dsi_packet_sent_handler_data *) data;
2382 if (dsi->data->quirks & DSI_QUIRK_VC_OCP_WIDTH)
2415 if (dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC) {
2539 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2625 u8 *data, u16 len, u8 ecc)
2646 p = data;
2688 u16 data, u8 ecc)
2698 data_type, data & 0xff, (data >> 8) & 0xff);
2709 r = (data_id << 0) | (data << 8) | (ecc << 24);
2722 u8 *data, int len,
2735 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
2741 data[0] | (data[1] << 8), 0);
2746 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
2753 u8 *data, int len)
2757 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2762 u8 *data, int len)
2766 return dsi_vc_write_nosync_common(dsi, channel, data, len,
2771 int channel, u8 *data, int len,
2777 r = dsi_vc_write_nosync_common(dsi, channel, data, len, type);
2787 DSSERR("rx fifo not empty after write, dumping data:\n");
2796 channel, data[0], len);
2800 static int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2803 return dsi_vc_write_common(dssdev, channel, data, len,
2807 static int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
2810 return dsi_vc_write_common(dssdev, channel, data, len,
2836 u16 data;
2846 data = 0;
2849 data = reqdata[0];
2852 data = reqdata[0] | (reqdata[1] << 8);
2858 r = dsi_vc_send_short(dsi, channel, data_type, data, 0);
2895 u8 data = FLD_GET(val, 15, 8);
2899 "DCS", data);
2906 buf[0] = data;
2912 u16 data = FLD_GET(val, 23, 8);
2916 "DCS", data);
2923 buf[0] = data & 0xff;
2924 buf[1] = (data >> 8) & 0xff;
3098 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3310 * results in maximum transition time for data and clock lanes to enter and
3312 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3313 * clock cycles that can be used to interleave command mode data in HS so that
3323 * time of data lanes only, if it isn't set, we need to consider HS
3324 * transition time of both data and clock lanes. HS transition time
3342 * results in maximum transition time for data lanes to enter and exit LP mode.
3343 * Hence, this is the scenario where the least amount of command mode data can
3354 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3531 if (!(dsi->data->quirks & DSI_QUIRK_DCS_CMD_CONFIG_VC)) {
3931 static void dsi_framedone_irq_callback(void *data)
3933 struct dsi_data *dsi = data;
3937 * and is sending the data.
3946 void (*callback)(int, void *), void *data)
3956 dsi->framedone_data = data;
4303 unsigned long pck, void *data)
4305 struct dsi_clk_calc_ctx *ctx = data;
4324 void *data)
4326 struct dsi_clk_calc_ctx *ctx = data;
4337 unsigned long clkdco, void *data)
4339 struct dsi_clk_calc_ctx *ctx = data;
4348 dsi->data->max_fck_freq,
4591 unsigned long pck, void *data)
4593 struct dsi_clk_calc_ctx *ctx = data;
4614 void *data)
4616 struct dsi_clk_calc_ctx *ctx = data;
4638 unsigned long clkdco, void *data)
4640 struct dsi_clk_calc_ctx *ctx = data;
4649 dsi->data->max_fck_freq,
4775 switch (dsi->data->model) {
5036 pll->hw = dsi->data->pll_hw;
5050 static int dsi_bind(struct device *dev, struct device *master, void *data)
5089 static void dsi_unbind(struct device *dev, struct device *master, void *data)
5163 dev_err(dsi->dev, "failed to find lane data\n");
5179 dev_err(dsi->dev, "failed to read lane data\n");
5255 { .compatible = "ti,omap3-dsi", .data = &dsi_of_data_omap36xx, },
5256 { .compatible = "ti,omap4-dsi", .data = &dsi_of_data_omap4, },
5257 { .compatible = "ti,omap5-dsi", .data = &dsi_of_data_omap5, },
5262 { .machine = "OMAP3[45]*", .data = &dsi_of_data_omap34xx },
5263 { .machine = "AM35*", .data = &dsi_of_data_omap34xx },
5341 dsi->data = soc->data;
5343 dsi->data = of_match_node(dsi_of_match, dev->of_node)->data;
5345 d = dsi->data->modules;
5356 if (dsi->data->model == DSI_MODEL_OMAP4 ||
5357 dsi->data->model == DSI_MODEL_OMAP5) {
5365 dsi->data->model == DSI_MODEL_OMAP4 ?
5388 * of data to 3 by default */
5389 if (dsi->data->quirks & DSI_QUIRK_GNQ) {
5410 DSSERR("Invalid DSI DT data\n");