Lines Matching refs:plane
174 /* maps which plane is using a fifo. fifo-id -> plane-id */
350 enum omap_plane_id plane);
352 enum omap_plane_id plane);
733 enum omap_plane_id plane = OMAP_DSS_WB;
736 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
751 enum omap_plane_id plane, int reg,
754 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value);
758 enum omap_plane_id plane, int reg,
761 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value);
765 enum omap_plane_id plane, int reg,
768 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value);
772 enum omap_plane_id plane, int reg,
775 BUG_ON(plane == OMAP_DSS_GFX);
777 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value);
781 enum omap_plane_id plane, int reg,
784 BUG_ON(plane == OMAP_DSS_GFX);
786 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
790 enum omap_plane_id plane, int reg,
793 BUG_ON(plane == OMAP_DSS_GFX);
795 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value);
799 enum omap_plane_id plane, int fir_hinc,
828 dispc_ovl_write_firh_reg(dispc, plane, i, h);
829 dispc_ovl_write_firhv_reg(dispc, plane, i, hv);
831 dispc_ovl_write_firh2_reg(dispc, plane, i, h);
832 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv);
843 dispc_ovl_write_firv_reg(dispc, plane, i, v);
845 dispc_ovl_write_firv2_reg(dispc, plane, i, v);
861 enum omap_plane_id plane,
866 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry));
867 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb));
868 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr));
869 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by));
870 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb));
872 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
880 const enum omap_plane_id plane = OMAP_DSS_WB;
884 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr));
885 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb));
886 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg));
887 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr));
888 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb));
890 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11);
924 enum omap_plane_id plane, u32 paddr)
926 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr);
930 enum omap_plane_id plane, u32 paddr)
932 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr);
936 enum omap_plane_id plane, u32 paddr)
938 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr);
942 enum omap_plane_id plane, u32 paddr)
944 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr);
948 enum omap_plane_id plane,
958 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val);
962 enum omap_plane_id plane, int width,
967 if (plane == OMAP_DSS_GFX || plane == OMAP_DSS_WB)
968 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
970 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
974 enum omap_plane_id plane, int width,
979 BUG_ON(plane == OMAP_DSS_GFX);
983 if (plane == OMAP_DSS_WB)
984 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val);
986 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val);
990 enum omap_plane_id plane,
996 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
1011 enum omap_plane_id plane,
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
1022 enum omap_plane_id plane,
1032 shift = shifts[plane];
1037 enum omap_plane_id plane, s32 inc)
1039 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc);
1043 enum omap_plane_id plane, s32 inc)
1045 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc);
1049 enum omap_plane_id plane, u32 fourcc)
1052 if (plane != OMAP_DSS_GFX) {
1118 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
1122 enum omap_plane_id plane,
1129 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
1131 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
1135 enum omap_plane_id plane,
1142 switch (plane) {
1156 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1194 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1198 enum omap_plane_id plane)
1203 switch (plane) {
1217 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1239 enum omap_plane_id plane,
1245 shift = shifts[plane];
1246 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size,
1263 enum omap_plane_id plane)
1270 enum omap_plane_id plane, u32 fourcc)
1275 modes = dispc->feat->supported_color_modes[plane];
1286 enum omap_plane_id plane)
1288 return dispc->feat->supported_color_modes[plane];
1322 enum omap_plane_id plane, bool enable)
1326 BUG_ON(plane == OMAP_DSS_GFX);
1328 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1330 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val);
1334 enum omap_plane_id plane,
1344 shift = shifts[plane];
1345 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1388 * giving GFX plane a larger fifo. WB but should work fine with a
1435 enum omap_plane_id plane)
1441 if (dispc->fifo_assignment[fifo] == plane)
1449 enum omap_plane_id plane,
1469 plane,
1470 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1472 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1476 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane),
1486 dispc->feat->set_max_preload && plane != OMAP_DSS_WB)
1487 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane),
1503 enum omap_plane_id plane,
1515 burst_size = dispc_ovl_get_burst_size(dispc, plane);
1516 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane);
1535 } else if (plane == OMAP_DSS_WB) {
1550 enum omap_plane_id plane, bool enable)
1554 if (plane == OMAP_DSS_GFX)
1559 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1563 enum omap_plane_id plane,
1566 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane),
1628 enum omap_plane_id plane,
1644 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val);
1647 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val);
1652 enum omap_plane_id plane, int haccu,
1666 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val);
1670 enum omap_plane_id plane, int haccu,
1684 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val);
1688 enum omap_plane_id plane, int haccu,
1694 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val);
1698 enum omap_plane_id plane, int haccu,
1704 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val);
1708 enum omap_plane_id plane,
1719 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps,
1721 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp);
1725 enum omap_plane_id plane,
1809 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0);
1810 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1);
1814 enum omap_plane_id plane,
1825 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1828 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
1849 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
1864 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0);
1865 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1);
1869 enum omap_plane_id plane,
1878 bool chroma_upscale = plane != OMAP_DSS_WB;
1888 if (plane != OMAP_DSS_WB)
1889 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1894 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width,
1937 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height,
1941 if (plane != OMAP_DSS_WB)
1942 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane),
1946 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1948 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1952 enum omap_plane_id plane,
1959 BUG_ON(plane == OMAP_DSS_GFX);
1961 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height,
1965 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height,
1971 enum omap_plane_id plane, u8 rotation,
2027 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
2029 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2032 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) {
2039 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane),
2482 enum omap_plane_id plane,
2515 if (plane == OMAP_DSS_WB) {
2591 enum omap_plane_id plane,
2615 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane);
2616 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane);
2622 if (plane == OMAP_DSS_WB)
2636 if (plane != OMAP_DSS_WB) {
2651 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc))
2654 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width,
2702 if (plane == OMAP_DSS_WB)
2716 dispc_ovl_set_color_mode(dispc, plane, fourcc);
2718 dispc_ovl_configure_burst_type(dispc, plane, rotation_type);
2723 dispc_ovl_set_ba0(dispc, plane, paddr + offset0);
2724 dispc_ovl_set_ba1(dispc, plane, paddr + offset1);
2727 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0);
2728 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1);
2734 dispc_ovl_set_row_inc(dispc, plane, row_inc);
2735 dispc_ovl_set_pix_inc(dispc, plane, pix_inc);
2740 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y);
2742 dispc_ovl_set_input_size(dispc, plane, in_width, in_height);
2745 dispc_ovl_set_scaling(dispc, plane, in_width, in_height,
2748 dispc_ovl_set_output_size(dispc, plane, out_width, out_height);
2749 dispc_ovl_set_vid_color_conv(dispc, plane, cconv);
2752 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type,
2755 dispc_ovl_set_zorder(dispc, plane, caps, zorder);
2756 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha);
2757 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha);
2759 dispc_ovl_enable_replication(dispc, plane, caps, replication);
2765 enum omap_plane_id plane,
2771 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane];
2776 plane, &oi->paddr, &oi->p_uv_addr, oi->screen_width, oi->pos_x,
2780 dispc_ovl_set_channel_out(dispc, plane, channel);
2782 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr,
2798 enum omap_plane_id plane = OMAP_DSS_WB;
2815 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr,
2840 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane));
2848 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l);
2852 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0);
2868 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0);
2880 enum omap_plane_id plane, bool enable)
2882 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2884 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
3349 enum omap_plane_id plane)
3353 if (plane == OMAP_DSS_WB)
3356 channel = dispc_ovl_get_channel_out(dispc, plane);
3362 enum omap_plane_id plane)
3366 if (plane == OMAP_DSS_WB)
3369 channel = dispc_ovl_get_channel_out(dispc, plane);
3587 #define DISPC_REG(plane, name, i) name(plane, i)
3588 #define DUMPREG(dispc, plane, name, i) \
3589 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3590 (int)(46 - strlen(#name) - strlen(p_names[plane])), " ", \
3591 dispc_read_reg(dispc, DISPC_REG(plane, name, i)))
4529 * For gamma tables to work on LCD1 the GFX plane has to be used at
4531 * sets up a minimal LCD setup with GFX plane and waits for one
4645 /* Setup and enable GFX plane */