Lines Matching defs:enable

628 	/* enable last, because LCD & DIGIT enable are here */
638 * enable last so IRQs won't trigger before
697 enum omap_channel channel, bool enable)
699 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable);
734 bool enable, go;
736 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1;
738 if (!enable)
1013 bool enable)
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
1292 enum omap_channel channel, bool enable)
1297 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable);
1322 enum omap_plane_id plane, bool enable)
1329 val = FLD_MOD(val, enable, 9, 9);
1336 bool enable)
1345 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1491 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable)
1494 WARN_ON(enable);
1498 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1499 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1550 enum omap_plane_id plane, bool enable)
1559 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
2880 enum omap_plane_id plane, bool enable)
2882 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2884 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2898 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable)
2903 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2906 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable)
2911 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2916 bool enable)
2918 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2952 enum omap_channel ch, bool enable)
2954 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable);
2959 bool enable)
2965 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18);
2967 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19);
3044 enum omap_channel channel, bool enable)
3046 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable);
3907 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
4645 /* Setup and enable GFX plane */
4650 /* Set up and enable display manager for LCD1 */