Lines Matching refs:args
151 struct nv_dma_v0 args = {};
210 args.target = NV_DMA_V0_TARGET_VM;
211 args.access = NV_DMA_V0_ACCESS_VM;
212 args.start = 0;
213 args.limit = chan->vmm->vmm.limit - 1;
221 args.target = NV_DMA_V0_TARGET_PCI;
222 args.access = NV_DMA_V0_ACCESS_RDWR;
223 args.start = nvxx_device(device)->func->
225 args.limit = args.start + device->info.ram_user - 1;
227 args.target = NV_DMA_V0_TARGET_VRAM;
228 args.access = NV_DMA_V0_ACCESS_RDWR;
229 args.start = 0;
230 args.limit = device->info.ram_user - 1;
234 args.target = NV_DMA_V0_TARGET_AGP;
235 args.access = NV_DMA_V0_ACCESS_RDWR;
236 args.start = chan->drm->agp.base;
237 args.limit = chan->drm->agp.base +
240 args.target = NV_DMA_V0_TARGET_VM;
241 args.access = NV_DMA_V0_ACCESS_RDWR;
242 args.start = 0;
243 args.limit = chan->vmm->vmm.limit - 1;
248 NV_DMA_FROM_MEMORY, &args, sizeof(args),
278 } args;
292 args.volta.version = 0;
293 args.volta.ilength = 0x02000;
294 args.volta.ioffset = 0x10000 + chan->push.addr;
295 args.volta.runlist = runlist;
296 args.volta.vmm = nvif_handle(&chan->vmm->vmm.object);
297 args.volta.priv = priv;
298 size = sizeof(args.volta);
301 args.kepler.version = 0;
302 args.kepler.ilength = 0x02000;
303 args.kepler.ioffset = 0x10000 + chan->push.addr;
304 args.kepler.runlist = runlist;
305 args.kepler.vmm = nvif_handle(&chan->vmm->vmm.object);
306 args.kepler.priv = priv;
307 size = sizeof(args.kepler);
310 args.fermi.version = 0;
311 args.fermi.ilength = 0x02000;
312 args.fermi.ioffset = 0x10000 + chan->push.addr;
313 args.fermi.vmm = nvif_handle(&chan->vmm->vmm.object);
314 size = sizeof(args.fermi);
316 args.nv50.version = 0;
317 args.nv50.ilength = 0x02000;
318 args.nv50.ioffset = 0x10000 + chan->push.addr;
319 args.nv50.pushbuf = nvif_handle(&chan->push.ctxdma);
320 args.nv50.vmm = nvif_handle(&chan->vmm->vmm.object);
321 size = sizeof(args.nv50);
325 *oclass++, &args, size, &chan->user);
328 chan->chid = args.volta.chid;
329 chan->inst = args.volta.inst;
330 chan->token = args.volta.token;
333 chan->chid = args.kepler.chid;
334 chan->inst = args.kepler.inst;
337 chan->chid = args.fermi.chid;
339 chan->chid = args.nv50.chid;
359 struct nv03_channel_dma_v0 args;
370 args.version = 0;
371 args.pushbuf = nvif_handle(&chan->push.ctxdma);
372 args.offset = chan->push.addr;
376 *oclass++, &args, sizeof(args),
379 chan->chid = args.chid;
393 struct nv_dma_v0 args = {};
415 args.target = NV_DMA_V0_TARGET_VM;
416 args.access = NV_DMA_V0_ACCESS_VM;
417 args.start = 0;
418 args.limit = chan->vmm->vmm.limit - 1;
420 args.target = NV_DMA_V0_TARGET_VRAM;
421 args.access = NV_DMA_V0_ACCESS_RDWR;
422 args.start = 0;
423 args.limit = device->info.ram_user - 1;
427 NV_DMA_IN_MEMORY, &args, sizeof(args),
433 args.target = NV_DMA_V0_TARGET_VM;
434 args.access = NV_DMA_V0_ACCESS_VM;
435 args.start = 0;
436 args.limit = chan->vmm->vmm.limit - 1;
439 args.target = NV_DMA_V0_TARGET_AGP;
440 args.access = NV_DMA_V0_ACCESS_RDWR;
441 args.start = chan->drm->agp.base;
442 args.limit = chan->drm->agp.base +
445 args.target = NV_DMA_V0_TARGET_VM;
446 args.access = NV_DMA_V0_ACCESS_RDWR;
447 args.start = 0;
448 args.limit = chan->vmm->vmm.limit - 1;
452 NV_DMA_IN_MEMORY, &args, sizeof(args),
556 } args = {
558 .m.count = sizeof(args.v) / sizeof(args.v.channels),
564 ret = nvif_object_mthd(device, NV_DEVICE_V0_INFO, &args, sizeof(args));
565 if (ret || args.v.channels.mthd == NV_DEVICE_INFO_INVALID)
568 drm->chan.nr = args.v.channels.data;