Lines Matching refs:head
39 NVWriteVgaSeq(struct drm_device *dev, int head, uint8_t index, uint8_t value)
41 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
42 NVWritePRMVIO(dev, head, NV_PRMVIO_SR, value);
46 NVReadVgaSeq(struct drm_device *dev, int head, uint8_t index)
48 NVWritePRMVIO(dev, head, NV_PRMVIO_SRX, index);
49 return NVReadPRMVIO(dev, head, NV_PRMVIO_SR);
53 NVWriteVgaGr(struct drm_device *dev, int head, uint8_t index, uint8_t value)
55 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
56 NVWritePRMVIO(dev, head, NV_PRMVIO_GX, value);
60 NVReadVgaGr(struct drm_device *dev, int head, uint8_t index)
62 NVWritePRMVIO(dev, head, NV_PRMVIO_GRX, index);
63 return NVReadPRMVIO(dev, head, NV_PRMVIO_GX);
66 /* CR44 takes values 0 (head A), 3 (head B) and 4 (heads tied)
70 * expected and values can be set for the appropriate head by using a 0x2000
73 * a) pre nv40, the head B range of PRMVIO regs at 0xc23c* was not exposed and
74 * cr44 must be set to 0 or 3 for accessing values on the correct head
76 * b) in tied mode (4) head B is programmed to the values set on head A, and
77 * access using the head B addresses can have strange results, ergo we leave
81 * 0 and 1 are treated as head values and so the set value is (owner * 3)
110 NVBlankScreen(struct drm_device *dev, int head, bool blank)
115 NVSetOwner(dev, head);
117 seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
119 NVVgaSeqReset(dev, head, true);
121 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
123 NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20);
124 NVVgaSeqReset(dev, head, false);
251 nouveau_hw_fix_bad_vpll(struct drm_device *dev, int head)
253 /* the vpll on an unused head can come up with a random value, way
265 enum nvbios_pll_type pll = head ? PLL_VPLL1 : PLL_VPLL0;
276 NV_WARN(drm, "VPLL %d outwith limits, attempting to fix\n", head + 1);
378 rd_cio_state(struct drm_device *dev, int head,
381 crtcstate->CRTC[index] = NVReadVgaCrtc(dev, head, index);
385 wr_cio_state(struct drm_device *dev, int head,
388 NVWriteVgaCrtc(dev, head, index, crtcstate->CRTC[index]);
392 nv_save_state_ramdac(struct drm_device *dev, int head,
396 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
400 regp->nv10_cursync = NVReadRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC);
402 nouveau_hw_get_pllvals(dev, head ? PLL_VPLL1 : PLL_VPLL0, ®p->pllvals);
407 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11);
409 regp->ramdac_gen_ctrl = NVReadRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL);
412 regp->ramdac_630 = NVReadRAMDAC(dev, head, NV_PRAMDAC_630);
414 regp->ramdac_634 = NVReadRAMDAC(dev, head, NV_PRAMDAC_634);
416 regp->tv_setup = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP);
417 regp->tv_vtotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL);
418 regp->tv_vskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW);
419 regp->tv_vsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY);
420 regp->tv_htotal = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL);
421 regp->tv_hskew = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW);
422 regp->tv_hsync_delay = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY);
423 regp->tv_hsync_delay2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2);
427 regp->fp_vert_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg);
428 regp->fp_horiz_regs[i] = NVReadRAMDAC(dev, head, ramdac_reg + 0x20);
432 regp->dither = NVReadRAMDAC(dev, head, NV_RAMDAC_FP_DITHER);
434 regp->dither_regs[i] = NVReadRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4);
435 regp->dither_regs[i + 3] = NVReadRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4);
439 regp->fp_control = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL);
440 regp->fp_debug_0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0);
441 if (!nv_gf4_disp_arch(dev) && head == 0) {
443 * the head A FPCLK on (nv11 even locks up) */
447 regp->fp_debug_1 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1);
448 regp->fp_debug_2 = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2);
450 regp->fp_margin_color = NVReadRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR);
453 regp->ramdac_8c0 = NVReadRAMDAC(dev, head, NV_PRAMDAC_8C0);
456 regp->ramdac_a20 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A20);
457 regp->ramdac_a24 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A24);
458 regp->ramdac_a34 = NVReadRAMDAC(dev, head, NV_PRAMDAC_A34);
461 regp->ctv_regs[i] = NVReadRAMDAC(dev, head,
467 nv_load_state_ramdac(struct drm_device *dev, int head,
472 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
473 uint32_t pllreg = head ? NV_RAMDAC_VPLL2 : NV_PRAMDAC_VPLL_COEFF;
477 NVWriteRAMDAC(dev, head, NV_RAMDAC_NV10_CURSYNC, regp->nv10_cursync);
484 NVWriteRAMDAC(dev, head, NV_RAMDAC_DITHER_NV11, regp->dither);
486 NVWriteRAMDAC(dev, head, NV_PRAMDAC_GENERAL_CONTROL, regp->ramdac_gen_ctrl);
489 NVWriteRAMDAC(dev, head, NV_PRAMDAC_630, regp->ramdac_630);
491 NVWriteRAMDAC(dev, head, NV_PRAMDAC_634, regp->ramdac_634);
493 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_SETUP, regp->tv_setup);
494 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VTOTAL, regp->tv_vtotal);
495 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSKEW, regp->tv_vskew);
496 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_VSYNC_DELAY, regp->tv_vsync_delay);
497 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HTOTAL, regp->tv_htotal);
498 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSKEW, regp->tv_hskew);
499 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY, regp->tv_hsync_delay);
500 NVWriteRAMDAC(dev, head, NV_PRAMDAC_TV_HSYNC_DELAY2, regp->tv_hsync_delay2);
505 NVWriteRAMDAC(dev, head, ramdac_reg, regp->fp_vert_regs[i]);
506 NVWriteRAMDAC(dev, head, ramdac_reg + 0x20, regp->fp_horiz_regs[i]);
510 NVWriteRAMDAC(dev, head, NV_RAMDAC_FP_DITHER, regp->dither);
512 NVWriteRAMDAC(dev, head, NV_PRAMDAC_850 + i * 4, regp->dither_regs[i]);
513 NVWriteRAMDAC(dev, head, NV_PRAMDAC_85C + i * 4, regp->dither_regs[i + 3]);
517 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_TG_CONTROL, regp->fp_control);
518 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_0, regp->fp_debug_0);
519 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_1, regp->fp_debug_1);
520 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_DEBUG_2, regp->fp_debug_2);
522 NVWriteRAMDAC(dev, head, NV_PRAMDAC_FP_MARGIN_COLOR, regp->fp_margin_color);
525 NVWriteRAMDAC(dev, head, NV_PRAMDAC_8C0, regp->ramdac_8c0);
528 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A20, regp->ramdac_a20);
529 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A24, regp->ramdac_a24);
530 NVWriteRAMDAC(dev, head, NV_PRAMDAC_A34, regp->ramdac_a34);
533 NVWriteRAMDAC(dev, head,
539 nv_save_state_vga(struct drm_device *dev, int head,
542 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
545 regp->MiscOutReg = NVReadPRMVIO(dev, head, NV_PRMVIO_MISC__READ);
548 rd_cio_state(dev, head, regp, i);
550 NVSetEnablePalette(dev, head, true);
552 regp->Attribute[i] = NVReadVgaAttr(dev, head, i);
553 NVSetEnablePalette(dev, head, false);
556 regp->Graphics[i] = NVReadVgaGr(dev, head, i);
559 regp->Sequencer[i] = NVReadVgaSeq(dev, head, i);
563 nv_load_state_vga(struct drm_device *dev, int head,
566 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
569 NVWritePRMVIO(dev, head, NV_PRMVIO_MISC__WRITE, regp->MiscOutReg);
572 NVWriteVgaSeq(dev, head, i, regp->Sequencer[i]);
574 nv_lock_vga_crtc_base(dev, head, false);
576 wr_cio_state(dev, head, regp, i);
577 nv_lock_vga_crtc_base(dev, head, true);
580 NVWriteVgaGr(dev, head, i, regp->Graphics[i]);
582 NVSetEnablePalette(dev, head, true);
584 NVWriteVgaAttr(dev, head, i, regp->Attribute[i]);
585 NVSetEnablePalette(dev, head, false);
589 nv_save_state_ext(struct drm_device *dev, int head,
593 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
596 rd_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
597 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
598 rd_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
599 rd_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
600 rd_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
601 rd_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
602 rd_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
604 rd_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
605 rd_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
606 rd_cio_state(dev, head, regp, NV_CIO_CRE_21);
609 rd_cio_state(dev, head, regp, NV_CIO_CRE_47);
612 rd_cio_state(dev, head, regp, 0x9f);
614 rd_cio_state(dev, head, regp, NV_CIO_CRE_49);
615 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
616 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
617 rd_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
618 rd_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
621 regp->crtc_830 = NVReadCRTC(dev, head, NV_PCRTC_830);
622 regp->crtc_834 = NVReadCRTC(dev, head, NV_PCRTC_834);
625 regp->gpio_ext = NVReadCRTC(dev, head, NV_PCRTC_GPIO_EXT);
628 regp->crtc_850 = NVReadCRTC(dev, head, NV_PCRTC_850);
631 regp->crtc_eng_ctrl = NVReadCRTC(dev, head, NV_PCRTC_ENGINE_CTRL);
632 regp->cursor_cfg = NVReadCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG);
635 regp->crtc_cfg = NVReadCRTC(dev, head, NV_PCRTC_CONFIG);
637 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
638 rd_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
640 rd_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
641 rd_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
642 rd_cio_state(dev, head, regp, NV_CIO_CRE_4B);
643 rd_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
647 rd_cio_state(dev, head, regp, NV_CIO_CRE_42);
648 rd_cio_state(dev, head, regp, NV_CIO_CRE_53);
649 rd_cio_state(dev, head, regp, NV_CIO_CRE_54);
652 regp->CR58[i] = NVReadVgaCrtc5758(dev, head, i);
653 rd_cio_state(dev, head, regp, NV_CIO_CRE_59);
654 rd_cio_state(dev, head, regp, NV_CIO_CRE_5B);
656 rd_cio_state(dev, head, regp, NV_CIO_CRE_85);
657 rd_cio_state(dev, head, regp, NV_CIO_CRE_86);
660 regp->fb_start = NVReadCRTC(dev, head, NV_PCRTC_START);
664 nv_load_state_ext(struct drm_device *dev, int head,
669 struct nv04_crtc_reg *regp = &state->crtc_reg[head];
679 NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
691 NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
692 NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
693 NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
696 NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
699 NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
701 reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
703 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
705 NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
709 NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
711 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
712 wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
713 wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
714 wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
715 wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
716 wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
717 wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
718 wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
719 wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
722 wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
725 wr_cio_state(dev, head, regp, 0x9f);
727 wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
728 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
729 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
730 wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
732 nv_fix_nv40_hw_cursor(dev, head);
733 wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
735 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
736 wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
738 wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
739 wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
740 wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
741 wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
758 wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
759 wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
760 wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
763 NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
764 wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
765 wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
767 wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
768 wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
771 NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
775 nv_save_state_palette(struct drm_device *dev, int head,
779 int head_offset = head * NV_PRMDIO_SIZE, i;
786 state->crtc_reg[head].DAC[i] = nvif_rd08(device,
790 NVSetEnablePalette(dev, head, false);
794 nouveau_hw_load_state_palette(struct drm_device *dev, int head,
798 int head_offset = head * NV_PRMDIO_SIZE, i;
806 state->crtc_reg[head].DAC[i]);
809 NVSetEnablePalette(dev, head, false);
812 void nouveau_hw_save_state(struct drm_device *dev, int head,
819 nouveau_hw_fix_bad_vpll(dev, head);
820 nv_save_state_ramdac(dev, head, state);
821 nv_save_state_vga(dev, head, state);
822 nv_save_state_palette(dev, head, state);
823 nv_save_state_ext(dev, head, state);
826 void nouveau_hw_load_state(struct drm_device *dev, int head,
829 NVVgaProtect(dev, head, true);
830 nv_load_state_ramdac(dev, head, state);
831 nv_load_state_ext(dev, head, state);
832 nouveau_hw_load_state_palette(dev, head, state);
833 nv_load_state_vga(dev, head, state);
834 NVVgaProtect(dev, head, false);