Lines Matching defs:mxsfb
5 * This code is based on drivers/video/fbdev/mxsfb.c :
40 static u32 set_hsync_pulse_width(struct mxsfb_drm_private *mxsfb, u32 val)
42 return (val & mxsfb->devdata->hs_wdth_mask) <<
43 mxsfb->devdata->hs_wdth_shift;
50 static void mxsfb_set_formats(struct mxsfb_drm_private *mxsfb)
52 struct drm_device *drm = mxsfb->drm;
53 const u32 format = mxsfb->crtc.primary->state->fb->format->format;
57 if (mxsfb->connector->display_info.num_bus_formats)
58 bus_format = mxsfb->connector->display_info.bus_formats[0];
66 ctrl1 = readl(mxsfb->base + LCDC_CTRL1);
98 writel(ctrl1, mxsfb->base + LCDC_CTRL1);
99 writel(ctrl, mxsfb->base + LCDC_CTRL);
102 static void mxsfb_enable_controller(struct mxsfb_drm_private *mxsfb)
106 if (mxsfb->clk_disp_axi)
107 clk_prepare_enable(mxsfb->clk_disp_axi);
108 clk_prepare_enable(mxsfb->clk);
111 if (mxsfb->devdata->has_ctrl2) {
112 reg = readl(mxsfb->base + LCDC_V4_CTRL2);
115 writel(reg, mxsfb->base + LCDC_V4_CTRL2);
119 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_SET);
122 reg = readl(mxsfb->base + LCDC_VDCTRL4);
124 writel(reg, mxsfb->base + LCDC_VDCTRL4);
151 reg = readl(mxsfb->base + LCDC_CTRL1);
153 writel(reg, mxsfb->base + LCDC_CTRL1);
155 writel(CTRL_RUN, mxsfb->base + LCDC_CTRL + REG_SET);
158 static void mxsfb_disable_controller(struct mxsfb_drm_private *mxsfb)
166 writel(CTRL_DOTCLK_MODE, mxsfb->base + LCDC_CTRL + REG_CLR);
168 readl_poll_timeout(mxsfb->base + LCDC_CTRL, reg, !(reg & CTRL_RUN),
171 reg = readl(mxsfb->base + LCDC_VDCTRL4);
173 writel(reg, mxsfb->base + LCDC_VDCTRL4);
175 clk_disable_unprepare(mxsfb->clk);
176 if (mxsfb->clk_disp_axi)
177 clk_disable_unprepare(mxsfb->clk_disp_axi);
193 static int mxsfb_reset_block(struct mxsfb_drm_private *mxsfb)
197 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST);
201 writel(CTRL_CLKGATE, mxsfb->base + LCDC_CTRL + REG_CLR);
203 ret = clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_SFTRST);
207 return clear_poll_bit(mxsfb->base + LCDC_CTRL, CTRL_CLKGATE);
225 static void mxsfb_crtc_mode_set_nofb(struct mxsfb_drm_private *mxsfb)
227 struct drm_device *drm = mxsfb->crtc.dev;
228 struct drm_display_mode *m = &mxsfb->crtc.state->adjusted_mode;
229 u32 bus_flags = mxsfb->connector->display_info.bus_flags;
240 err = mxsfb_reset_block(mxsfb);
245 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_SET);
246 readl(mxsfb->base + LCDC_CTRL1);
247 writel(CTRL1_FIFO_CLEAR, mxsfb->base + LCDC_CTRL1 + REG_CLR);
248 readl(mxsfb->base + LCDC_CTRL1);
250 if (mxsfb->devdata->has_overlay)
251 writel(0, mxsfb->base + LCDC_AS_CTRL);
253 mxsfb_set_formats(mxsfb);
255 clk_set_rate(mxsfb->clk, m->crtc_clock * 1000);
257 if (mxsfb->bridge && mxsfb->bridge->timings)
258 bus_flags = mxsfb->bridge->timings->input_bus_flags;
262 (int)(clk_get_rate(mxsfb->clk) / 1000));
269 mxsfb->base + mxsfb->devdata->transfer_count);
293 writel(vdctrl0, mxsfb->base + LCDC_VDCTRL0);
296 writel(m->crtc_vtotal, mxsfb->base + LCDC_VDCTRL1);
300 writel(set_hsync_pulse_width(mxsfb, hsync_pulse_len) |
302 mxsfb->base + LCDC_VDCTRL2);
306 mxsfb->base + LCDC_VDCTRL3);
309 mxsfb->base + LCDC_VDCTRL4);
348 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
349 struct drm_device *drm = mxsfb->drm;
353 mxsfb_enable_axi_clk(mxsfb);
357 mxsfb_crtc_mode_set_nofb(mxsfb);
362 writel(paddr, mxsfb->base + mxsfb->devdata->cur_buf);
363 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
366 mxsfb_enable_controller(mxsfb);
372 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
373 struct drm_device *drm = mxsfb->drm;
376 mxsfb_disable_controller(mxsfb);
388 mxsfb_disable_axi_clk(mxsfb);
394 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
397 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
398 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_SET);
405 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(crtc->dev);
408 writel(CTRL1_CUR_FRAME_DONE_IRQ_EN, mxsfb->base + LCDC_CTRL1 + REG_CLR);
409 writel(CTRL1_CUR_FRAME_DONE_IRQ, mxsfb->base + LCDC_CTRL1 + REG_CLR);
445 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
449 &mxsfb->crtc);
460 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
465 writel(paddr, mxsfb->base + mxsfb->devdata->next_buf);
471 struct mxsfb_drm_private *mxsfb = to_mxsfb_drm_private(plane->dev);
478 writel(0, mxsfb->base + LCDC_AS_CTRL);
490 writel(paddr, mxsfb->base + LCDC_AS_NEXT_BUF);
497 writel(paddr, mxsfb->base + LCDC_AS_BUF);
525 writel(ctrl, mxsfb->base + LCDC_AS_CTRL);
581 int mxsfb_kms_init(struct mxsfb_drm_private *mxsfb)
583 struct drm_encoder *encoder = &mxsfb->encoder;
584 struct drm_crtc *crtc = &mxsfb->crtc;
587 drm_plane_helper_add(&mxsfb->planes.primary,
589 ret = drm_universal_plane_init(mxsfb->drm, &mxsfb->planes.primary, 1,
598 if (mxsfb->devdata->has_overlay) {
599 drm_plane_helper_add(&mxsfb->planes.overlay,
601 ret = drm_universal_plane_init(mxsfb->drm,
602 &mxsfb->planes.overlay, 1,
613 ret = drm_crtc_init_with_planes(mxsfb->drm, crtc,
614 &mxsfb->planes.primary, NULL,
620 return drm_encoder_init(mxsfb->drm, encoder, &mxsfb_encoder_funcs,