Lines Matching defs:priv
36 void meson_vpp_setup_mux(struct meson_drm *priv, unsigned int mux)
38 writel(mux, priv->io_base + _REG(VPU_VIU_VENC_MUX_CTRL));
53 static void meson_vpp_write_scaling_filter_coefs(struct meson_drm *priv,
60 priv->io_base + _REG(VPP_OSD_SCALE_COEF_IDX));
63 priv->io_base + _REG(VPP_OSD_SCALE_COEF));
78 static void meson_vpp_write_vd_scaling_filter_coefs(struct meson_drm *priv,
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX));
88 priv->io_base + _REG(VPP_SCALE_COEF));
91 void meson_vpp_init(struct meson_drm *priv)
94 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXL))
95 writel_relaxed(0x108080, priv->io_base + _REG(VPP_DUMMY_DATA1));
96 else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
98 priv->io_base + _REG(VIU_MISC_CTRL1));
100 priv->io_base + _REG(VPP_DOLBY_CTRL));
102 priv->io_base + _REG(VPP_DUMMY_DATA1));
104 priv->io_base + _REG(VPP_DUMMY_DATA));
105 } else if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
106 writel_relaxed(0xf, priv->io_base + _REG(DOLBY_PATH_CTRL));
109 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A))
111 priv->io_base + _REG(VPP_OFIFO_SIZE));
114 priv->io_base + _REG(VPP_OFIFO_SIZE));
116 priv->io_base + _REG(VPP_HOLD_LINES));
118 if (!meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
121 priv->io_base + _REG(VPP_MISC));
125 priv->io_base + _REG(VPP_MISC));
131 priv->io_base + _REG(VPP_MISC));
135 priv->io_base + _REG(VPP_PREBLEND_VD1_H_START_END));
137 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
141 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
142 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
143 writel_relaxed(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
148 priv->io_base + _REG(VPP_SC_MISC));
152 priv->io_base + _REG(VPP_VADJ_CTRL));
155 meson_vpp_write_scaling_filter_coefs(priv,
157 meson_vpp_write_scaling_filter_coefs(priv,
161 meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,
163 meson_vpp_write_vd_scaling_filter_coefs(priv, vpp_filter_coefs_bicubic,