Lines Matching refs:viu
114 line_stride = ((priv->viu.osd1_width << 4) + 127) >> 7;
121 line_stride = ((priv->viu.osd1_width << 5) + 127) >> 7;
160 priv->viu.osd1_afbcd = true;
162 priv->viu.osd1_afbcd = false;
165 priv->viu.osd1_ctrl_stat = OSD_ENABLE |
169 priv->viu.osd1_ctrl_stat2 = readl(priv->io_base +
175 priv->viu.osd1_blk0_cfg[0] = canvas_id_osd1 << OSD_CANVAS_SEL;
177 if (priv->viu.osd1_afbcd) {
180 priv->viu.osd1_blk1_cfg4 = MESON_G12A_AFBCD_OUT_ADDR;
181 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_BE;
182 priv->viu.osd1_ctrl_stat2 |= OSD_PENDING_STAT_CLEAN;
183 priv->viu.osd1_ctrl_stat |= VIU_OSD1_CFG_SYN_EN;
187 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
188 priv->viu.osd1_ctrl_stat2 |= OSD_DPATH_MALI_AFBCD;
191 priv->viu.osd1_blk0_cfg[0] |= OSD_ENDIANNESS_LE;
194 priv->viu.osd1_ctrl_stat2 &= ~OSD_DPATH_MALI_AFBCD;
199 priv->viu.osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
201 if (priv->viu.osd1_afbcd &&
203 priv->viu.osd1_blk0_cfg[0] |= OSD_MALI_SRC_EN |
210 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
215 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
219 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_24 |
223 priv->viu.osd1_blk0_cfg[0] |= OSD_BLK_MODE_16 |
233 priv->viu.osd1_ctrl_stat2 |= OSD_REPLACE_EN;
238 priv->viu.osd1_ctrl_stat2 &= ~OSD_REPLACE_EN;
288 priv->viu.osd_sc_i_wh_m1 = SCI_WH_M1_W(src_w - 1) |
290 priv->viu.osd_sc_o_h_start_end = SCO_HV_START(dest.x1) |
292 priv->viu.osd_sc_o_v_start_end = SCO_HV_START(dest.y1) |
295 priv->viu.osd_sc_ctrl0 = SC_CTRL0_PATH_EN | SC_CTRL0_SEL_OSD1;
297 priv->viu.osd_sc_i_wh_m1 = 0;
298 priv->viu.osd_sc_o_h_start_end = 0;
299 priv->viu.osd_sc_o_v_start_end = 0;
300 priv->viu.osd_sc_ctrl0 = 0;
305 priv->viu.osd_sc_v_ctrl0 =
312 priv->viu.osd_sc_v_ctrl0 |=
317 priv->viu.osd_sc_v_phase_step = SC_PHASE_STEP(vf_phase_step);
318 priv->viu.osd_sc_v_ini_phase = VSC_INI_PHASE_BOT(bot_ini_phase);
320 priv->viu.osd_sc_v_ctrl0 = 0;
321 priv->viu.osd_sc_v_phase_step = 0;
322 priv->viu.osd_sc_v_ini_phase = 0;
327 priv->viu.osd_sc_h_ctrl0 =
332 priv->viu.osd_sc_h_phase_step = SC_PHASE_STEP(hf_phase_step);
333 priv->viu.osd_sc_h_ini_phase = 0;
335 priv->viu.osd_sc_h_ctrl0 = 0;
336 priv->viu.osd_sc_h_phase_step = 0;
337 priv->viu.osd_sc_h_ini_phase = 0;
345 priv->viu.osd1_blk0_cfg[1] =
348 priv->viu.osd1_blk0_cfg[2] =
351 priv->viu.osd1_blk0_cfg[3] = ((dest.x2 - 1) << 16) | dest.x1;
352 priv->viu.osd1_blk0_cfg[4] = ((dest.y2 - 1) << 16) | dest.y1;
355 priv->viu.osd_blend_din0_scope_h = ((dest.x2 - 1) << 16) | dest.x1;
356 priv->viu.osd_blend_din0_scope_v = ((dest.y2 - 1) << 16) | dest.y1;
357 priv->viu.osb_blend0_size = dst_h << 16 | dst_w;
358 priv->viu.osb_blend1_size = dst_h << 16 | dst_w;
364 priv->viu.osd1_addr = gem->paddr;
365 priv->viu.osd1_stride = fb->pitches[0];
366 priv->viu.osd1_height = fb->height;
367 priv->viu.osd1_width = fb->width;
369 if (priv->viu.osd1_afbcd) {
375 priv->viu.osd1_blk2_cfg4 =
388 priv->viu.osd1_enabled = true;
413 priv->viu.osd1_enabled = false;