Lines Matching refs:viu
158 priv->viu.osd1_enabled = false;
159 priv->viu.osd1_commit = false;
161 priv->viu.vd1_enabled = false;
162 priv->viu.vd1_commit = false;
183 priv->viu.osd1_enabled = false;
184 priv->viu.osd1_commit = false;
186 priv->viu.vd1_enabled = false;
187 priv->viu.vd1_commit = false;
225 priv->viu.osd1_commit = true;
226 priv->viu.vd1_commit = true;
251 writel_relaxed(priv->viu.osd1_blk2_cfg4,
257 writel_relaxed(priv->viu.osd1_blk1_cfg4,
271 writel_relaxed(priv->viu.osd_blend_din0_scope_h,
274 writel_relaxed(priv->viu.osd_blend_din0_scope_v,
277 writel_relaxed(priv->viu.osb_blend0_size,
280 writel_relaxed(priv->viu.osb_blend1_size,
296 priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0,
308 writel_relaxed(priv->viu.vd1_afbc ?
319 if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
320 writel_relaxed(priv->viu.osd1_ctrl_stat,
322 writel_relaxed(priv->viu.osd1_ctrl_stat2,
324 writel_relaxed(priv->viu.osd1_blk0_cfg[0],
326 writel_relaxed(priv->viu.osd1_blk0_cfg[1],
328 writel_relaxed(priv->viu.osd1_blk0_cfg[2],
330 writel_relaxed(priv->viu.osd1_blk0_cfg[3],
332 writel_relaxed(priv->viu.osd1_blk0_cfg[4],
335 if (priv->viu.osd1_afbcd) {
348 writel_relaxed(priv->viu.osd_sc_ctrl0,
350 writel_relaxed(priv->viu.osd_sc_i_wh_m1,
352 writel_relaxed(priv->viu.osd_sc_o_h_start_end,
354 writel_relaxed(priv->viu.osd_sc_o_v_start_end,
356 writel_relaxed(priv->viu.osd_sc_v_ini_phase,
358 writel_relaxed(priv->viu.osd_sc_v_phase_step,
360 writel_relaxed(priv->viu.osd_sc_h_ini_phase,
362 writel_relaxed(priv->viu.osd_sc_h_phase_step,
364 writel_relaxed(priv->viu.osd_sc_h_ctrl0,
366 writel_relaxed(priv->viu.osd_sc_v_ctrl0,
369 if (!priv->viu.osd1_afbcd)
371 priv->viu.osd1_addr,
372 priv->viu.osd1_stride,
373 priv->viu.osd1_height,
381 if (priv->viu.osd1_afbcd) {
388 priv->viu.osd1_commit = false;
392 if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
394 if (priv->viu.vd1_afbc) {
395 writel_relaxed(priv->viu.vd1_afbc_head_addr,
398 writel_relaxed(priv->viu.vd1_afbc_body_addr,
401 writel_relaxed(priv->viu.vd1_afbc_en,
404 writel_relaxed(priv->viu.vd1_afbc_mode,
407 writel_relaxed(priv->viu.vd1_afbc_size_in,
410 writel_relaxed(priv->viu.vd1_afbc_dec_def_color,
413 writel_relaxed(priv->viu.vd1_afbc_conv_ctrl,
416 writel_relaxed(priv->viu.vd1_afbc_size_out,
419 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl,
422 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w,
425 writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope,
428 writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope,
431 writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope,
434 writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope,
437 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h,
441 switch (priv->viu.vd1_planes) {
445 priv->viu.vd1_addr2,
446 priv->viu.vd1_stride2,
447 priv->viu.vd1_height2,
455 priv->viu.vd1_addr1,
456 priv->viu.vd1_stride1,
457 priv->viu.vd1_height1,
465 priv->viu.vd1_addr0,
466 priv->viu.vd1_stride0,
467 priv->viu.vd1_height0,
476 writel_relaxed(priv->viu.vd1_if0_gen_reg,
479 writel_relaxed(priv->viu.vd1_if0_gen_reg,
482 writel_relaxed(priv->viu.vd1_if0_gen_reg2,
485 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
488 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
491 writel_relaxed(priv->viu.viu_vd1_fmt_w,
494 writel_relaxed(priv->viu.viu_vd1_fmt_w,
497 writel_relaxed(priv->viu.vd1_if0_canvas0,
500 writel_relaxed(priv->viu.vd1_if0_canvas0,
503 writel_relaxed(priv->viu.vd1_if0_canvas0,
506 writel_relaxed(priv->viu.vd1_if0_canvas0,
509 writel_relaxed(priv->viu.vd1_if0_luma_x0,
512 writel_relaxed(priv->viu.vd1_if0_luma_x0,
515 writel_relaxed(priv->viu.vd1_if0_luma_x0,
518 writel_relaxed(priv->viu.vd1_if0_luma_x0,
521 writel_relaxed(priv->viu.vd1_if0_luma_y0,
524 writel_relaxed(priv->viu.vd1_if0_luma_y0,
527 writel_relaxed(priv->viu.vd1_if0_luma_y0,
530 writel_relaxed(priv->viu.vd1_if0_luma_y0,
533 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
536 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
539 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
542 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
545 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
548 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
551 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
554 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
557 writel_relaxed(priv->viu.vd1_if0_repeat_loop,
560 writel_relaxed(priv->viu.vd1_if0_repeat_loop,
563 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
566 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
569 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
572 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
575 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
578 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
581 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
584 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
595 writel_relaxed(priv->viu.vd1_range_map_y,
598 writel_relaxed(priv->viu.vd1_range_map_cb,
601 writel_relaxed(priv->viu.vd1_range_map_cr,
611 writel_relaxed(priv->viu.vpp_pic_in_height,
613 writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
615 writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
617 writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
619 writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
621 writel_relaxed(priv->viu.vpp_hsc_region12_startp,
623 writel_relaxed(priv->viu.vpp_hsc_region34_startp,
625 writel_relaxed(priv->viu.vpp_hsc_region4_endp,
627 writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
629 writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
631 writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
633 writel_relaxed(priv->viu.vpp_line_in_length,
635 writel_relaxed(priv->viu.vpp_preblend_h_size,
637 writel_relaxed(priv->viu.vpp_vsc_region12_startp,
639 writel_relaxed(priv->viu.vpp_vsc_region34_startp,
641 writel_relaxed(priv->viu.vpp_vsc_region4_endp,
643 writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
645 writel_relaxed(priv->viu.vpp_vsc_ini_phase,
647 writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
649 writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
657 priv->viu.vd1_commit = false;