Lines Matching refs:priv
37 struct meson_drm *priv;
38 void (*enable_osd1)(struct meson_drm *priv);
39 void (*enable_vd1)(struct meson_drm *priv);
40 void (*enable_osd1_afbc)(struct meson_drm *priv);
41 void (*disable_osd1_afbc)(struct meson_drm *priv);
53 struct meson_drm *priv = meson_crtc->priv;
56 meson_venc_enable_vsync(priv);
64 struct meson_drm *priv = meson_crtc->priv;
68 meson_venc_disable_vsync(priv);
89 struct meson_drm *priv = meson_crtc->priv;
100 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
105 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
109 priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE));
112 priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE));
115 priv->io_base + _REG(VPP_OUT_H_V_SIZE));
125 struct meson_drm *priv = meson_crtc->priv;
136 priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
140 priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
143 priv->io_base + _REG(VPP_MISC));
152 struct meson_drm *priv = meson_crtc->priv;
158 priv->viu.osd1_enabled = false;
159 priv->viu.osd1_commit = false;
161 priv->viu.vd1_enabled = false;
162 priv->viu.vd1_commit = false;
177 struct meson_drm *priv = meson_crtc->priv;
183 priv->viu.osd1_enabled = false;
184 priv->viu.osd1_commit = false;
186 priv->viu.vd1_enabled = false;
187 priv->viu.vd1_commit = false;
192 priv->io_base + _REG(VPP_MISC));
223 struct meson_drm *priv = meson_crtc->priv;
225 priv->viu.osd1_commit = true;
226 priv->viu.vd1_commit = true;
243 static void meson_crtc_enable_osd1(struct meson_drm *priv)
246 priv->io_base + _REG(VPP_MISC));
249 static void meson_crtc_g12a_enable_osd1_afbc(struct meson_drm *priv)
251 writel_relaxed(priv->viu.osd1_blk2_cfg4,
252 priv->io_base + _REG(VIU_OSD1_BLK2_CFG_W4));
255 priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
257 writel_relaxed(priv->viu.osd1_blk1_cfg4,
258 priv->io_base + _REG(VIU_OSD1_BLK1_CFG_W4));
260 meson_viu_g12a_enable_osd1_afbc(priv);
263 priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
266 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
269 static void meson_g12a_crtc_enable_osd1(struct meson_drm *priv)
271 writel_relaxed(priv->viu.osd_blend_din0_scope_h,
272 priv->io_base +
274 writel_relaxed(priv->viu.osd_blend_din0_scope_v,
275 priv->io_base +
277 writel_relaxed(priv->viu.osb_blend0_size,
278 priv->io_base +
280 writel_relaxed(priv->viu.osb_blend1_size,
281 priv->io_base +
284 priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
287 static void meson_crtc_enable_vd1(struct meson_drm *priv)
293 priv->io_base + _REG(VPP_MISC));
296 priv->viu.vd1_afbc ? VIU_CTRL0_AFBC_TO_VD1 : 0,
297 priv->io_base + _REG(VIU_MISC_CTRL0));
300 static void meson_g12a_crtc_enable_vd1(struct meson_drm *priv)
306 priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
308 writel_relaxed(priv->viu.vd1_afbc ?
310 priv->io_base + _REG(VD1_AFBCD0_MISC_CTRL));
313 void meson_crtc_irq(struct meson_drm *priv)
315 struct meson_crtc *meson_crtc = to_meson_crtc(priv->crtc);
319 if (priv->viu.osd1_enabled && priv->viu.osd1_commit) {
320 writel_relaxed(priv->viu.osd1_ctrl_stat,
321 priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
322 writel_relaxed(priv->viu.osd1_ctrl_stat2,
323 priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
324 writel_relaxed(priv->viu.osd1_blk0_cfg[0],
325 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
326 writel_relaxed(priv->viu.osd1_blk0_cfg[1],
327 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
328 writel_relaxed(priv->viu.osd1_blk0_cfg[2],
329 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
330 writel_relaxed(priv->viu.osd1_blk0_cfg[3],
331 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
332 writel_relaxed(priv->viu.osd1_blk0_cfg[4],
333 priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
335 if (priv->viu.osd1_afbcd) {
337 meson_crtc->enable_osd1_afbc(priv);
340 meson_crtc->disable_osd1_afbc(priv);
341 if (priv->afbcd.ops) {
342 priv->afbcd.ops->reset(priv);
343 priv->afbcd.ops->disable(priv);
348 writel_relaxed(priv->viu.osd_sc_ctrl0,
349 priv->io_base + _REG(VPP_OSD_SC_CTRL0));
350 writel_relaxed(priv->viu.osd_sc_i_wh_m1,
351 priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
352 writel_relaxed(priv->viu.osd_sc_o_h_start_end,
353 priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
354 writel_relaxed(priv->viu.osd_sc_o_v_start_end,
355 priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
356 writel_relaxed(priv->viu.osd_sc_v_ini_phase,
357 priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
358 writel_relaxed(priv->viu.osd_sc_v_phase_step,
359 priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
360 writel_relaxed(priv->viu.osd_sc_h_ini_phase,
361 priv->io_base + _REG(VPP_OSD_HSC_INI_PHASE));
362 writel_relaxed(priv->viu.osd_sc_h_phase_step,
363 priv->io_base + _REG(VPP_OSD_HSC_PHASE_STEP));
364 writel_relaxed(priv->viu.osd_sc_h_ctrl0,
365 priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
366 writel_relaxed(priv->viu.osd_sc_v_ctrl0,
367 priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
369 if (!priv->viu.osd1_afbcd)
370 meson_canvas_config(priv->canvas, priv->canvas_id_osd1,
371 priv->viu.osd1_addr,
372 priv->viu.osd1_stride,
373 priv->viu.osd1_height,
379 meson_crtc->enable_osd1(priv);
381 if (priv->viu.osd1_afbcd) {
382 priv->afbcd.ops->reset(priv);
383 priv->afbcd.ops->setup(priv);
384 priv->afbcd.ops->enable(priv);
388 priv->viu.osd1_commit = false;
392 if (priv->viu.vd1_enabled && priv->viu.vd1_commit) {
394 if (priv->viu.vd1_afbc) {
395 writel_relaxed(priv->viu.vd1_afbc_head_addr,
396 priv->io_base +
398 writel_relaxed(priv->viu.vd1_afbc_body_addr,
399 priv->io_base +
401 writel_relaxed(priv->viu.vd1_afbc_en,
402 priv->io_base +
404 writel_relaxed(priv->viu.vd1_afbc_mode,
405 priv->io_base +
407 writel_relaxed(priv->viu.vd1_afbc_size_in,
408 priv->io_base +
410 writel_relaxed(priv->viu.vd1_afbc_dec_def_color,
411 priv->io_base +
413 writel_relaxed(priv->viu.vd1_afbc_conv_ctrl,
414 priv->io_base +
416 writel_relaxed(priv->viu.vd1_afbc_size_out,
417 priv->io_base +
419 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_ctrl,
420 priv->io_base +
422 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_w,
423 priv->io_base +
425 writel_relaxed(priv->viu.vd1_afbc_mif_hor_scope,
426 priv->io_base +
428 writel_relaxed(priv->viu.vd1_afbc_mif_ver_scope,
429 priv->io_base +
431 writel_relaxed(priv->viu.vd1_afbc_pixel_hor_scope,
432 priv->io_base+
434 writel_relaxed(priv->viu.vd1_afbc_pixel_ver_scope,
435 priv->io_base +
437 writel_relaxed(priv->viu.vd1_afbc_vd_cfmt_h,
438 priv->io_base +
441 switch (priv->viu.vd1_planes) {
443 meson_canvas_config(priv->canvas,
444 priv->canvas_id_vd1_2,
445 priv->viu.vd1_addr2,
446 priv->viu.vd1_stride2,
447 priv->viu.vd1_height2,
453 meson_canvas_config(priv->canvas,
454 priv->canvas_id_vd1_1,
455 priv->viu.vd1_addr1,
456 priv->viu.vd1_stride1,
457 priv->viu.vd1_height1,
463 meson_canvas_config(priv->canvas,
464 priv->canvas_id_vd1_0,
465 priv->viu.vd1_addr0,
466 priv->viu.vd1_stride0,
467 priv->viu.vd1_height0,
473 writel_relaxed(0, priv->io_base + _REG(AFBC_ENABLE));
476 writel_relaxed(priv->viu.vd1_if0_gen_reg,
477 priv->io_base + meson_crtc->viu_offset +
479 writel_relaxed(priv->viu.vd1_if0_gen_reg,
480 priv->io_base + meson_crtc->viu_offset +
482 writel_relaxed(priv->viu.vd1_if0_gen_reg2,
483 priv->io_base + meson_crtc->viu_offset +
485 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
486 priv->io_base + meson_crtc->viu_offset +
488 writel_relaxed(priv->viu.viu_vd1_fmt_ctrl,
489 priv->io_base + meson_crtc->viu_offset +
491 writel_relaxed(priv->viu.viu_vd1_fmt_w,
492 priv->io_base + meson_crtc->viu_offset +
494 writel_relaxed(priv->viu.viu_vd1_fmt_w,
495 priv->io_base + meson_crtc->viu_offset +
497 writel_relaxed(priv->viu.vd1_if0_canvas0,
498 priv->io_base + meson_crtc->viu_offset +
500 writel_relaxed(priv->viu.vd1_if0_canvas0,
501 priv->io_base + meson_crtc->viu_offset +
503 writel_relaxed(priv->viu.vd1_if0_canvas0,
504 priv->io_base + meson_crtc->viu_offset +
506 writel_relaxed(priv->viu.vd1_if0_canvas0,
507 priv->io_base + meson_crtc->viu_offset +
509 writel_relaxed(priv->viu.vd1_if0_luma_x0,
510 priv->io_base + meson_crtc->viu_offset +
512 writel_relaxed(priv->viu.vd1_if0_luma_x0,
513 priv->io_base + meson_crtc->viu_offset +
515 writel_relaxed(priv->viu.vd1_if0_luma_x0,
516 priv->io_base + meson_crtc->viu_offset +
518 writel_relaxed(priv->viu.vd1_if0_luma_x0,
519 priv->io_base + meson_crtc->viu_offset +
521 writel_relaxed(priv->viu.vd1_if0_luma_y0,
522 priv->io_base + meson_crtc->viu_offset +
524 writel_relaxed(priv->viu.vd1_if0_luma_y0,
525 priv->io_base + meson_crtc->viu_offset +
527 writel_relaxed(priv->viu.vd1_if0_luma_y0,
528 priv->io_base + meson_crtc->viu_offset +
530 writel_relaxed(priv->viu.vd1_if0_luma_y0,
531 priv->io_base + meson_crtc->viu_offset +
533 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
534 priv->io_base + meson_crtc->viu_offset +
536 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
537 priv->io_base + meson_crtc->viu_offset +
539 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
540 priv->io_base + meson_crtc->viu_offset +
542 writel_relaxed(priv->viu.vd1_if0_chroma_x0,
543 priv->io_base + meson_crtc->viu_offset +
545 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
546 priv->io_base + meson_crtc->viu_offset +
548 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
549 priv->io_base + meson_crtc->viu_offset +
551 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
552 priv->io_base + meson_crtc->viu_offset +
554 writel_relaxed(priv->viu.vd1_if0_chroma_y0,
555 priv->io_base + meson_crtc->viu_offset +
557 writel_relaxed(priv->viu.vd1_if0_repeat_loop,
558 priv->io_base + meson_crtc->viu_offset +
560 writel_relaxed(priv->viu.vd1_if0_repeat_loop,
561 priv->io_base + meson_crtc->viu_offset +
563 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
564 priv->io_base + meson_crtc->viu_offset +
566 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
567 priv->io_base + meson_crtc->viu_offset +
569 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
570 priv->io_base + meson_crtc->viu_offset +
572 writel_relaxed(priv->viu.vd1_if0_luma0_rpt_pat,
573 priv->io_base + meson_crtc->viu_offset +
575 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
576 priv->io_base + meson_crtc->viu_offset +
578 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
579 priv->io_base + meson_crtc->viu_offset +
581 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
582 priv->io_base + meson_crtc->viu_offset +
584 writel_relaxed(priv->viu.vd1_if0_chroma0_rpt_pat,
585 priv->io_base + meson_crtc->viu_offset +
587 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
589 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
591 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
593 writel_relaxed(0, priv->io_base + meson_crtc->viu_offset +
595 writel_relaxed(priv->viu.vd1_range_map_y,
596 priv->io_base + meson_crtc->viu_offset +
598 writel_relaxed(priv->viu.vd1_range_map_cb,
599 priv->io_base + meson_crtc->viu_offset +
601 writel_relaxed(priv->viu.vd1_range_map_cr,
602 priv->io_base + meson_crtc->viu_offset +
610 priv->io_base + _REG(VPP_SC_MISC));
611 writel_relaxed(priv->viu.vpp_pic_in_height,
612 priv->io_base + _REG(VPP_PIC_IN_HEIGHT));
613 writel_relaxed(priv->viu.vpp_postblend_vd1_h_start_end,
614 priv->io_base + _REG(VPP_POSTBLEND_VD1_H_START_END));
615 writel_relaxed(priv->viu.vpp_blend_vd2_h_start_end,
616 priv->io_base + _REG(VPP_BLEND_VD2_H_START_END));
617 writel_relaxed(priv->viu.vpp_postblend_vd1_v_start_end,
618 priv->io_base + _REG(VPP_POSTBLEND_VD1_V_START_END));
619 writel_relaxed(priv->viu.vpp_blend_vd2_v_start_end,
620 priv->io_base + _REG(VPP_BLEND_VD2_V_START_END));
621 writel_relaxed(priv->viu.vpp_hsc_region12_startp,
622 priv->io_base + _REG(VPP_HSC_REGION12_STARTP));
623 writel_relaxed(priv->viu.vpp_hsc_region34_startp,
624 priv->io_base + _REG(VPP_HSC_REGION34_STARTP));
625 writel_relaxed(priv->viu.vpp_hsc_region4_endp,
626 priv->io_base + _REG(VPP_HSC_REGION4_ENDP));
627 writel_relaxed(priv->viu.vpp_hsc_start_phase_step,
628 priv->io_base + _REG(VPP_HSC_START_PHASE_STEP));
629 writel_relaxed(priv->viu.vpp_hsc_region1_phase_slope,
630 priv->io_base + _REG(VPP_HSC_REGION1_PHASE_SLOPE));
631 writel_relaxed(priv->viu.vpp_hsc_region3_phase_slope,
632 priv->io_base + _REG(VPP_HSC_REGION3_PHASE_SLOPE));
633 writel_relaxed(priv->viu.vpp_line_in_length,
634 priv->io_base + _REG(VPP_LINE_IN_LENGTH));
635 writel_relaxed(priv->viu.vpp_preblend_h_size,
636 priv->io_base + _REG(VPP_PREBLEND_H_SIZE));
637 writel_relaxed(priv->viu.vpp_vsc_region12_startp,
638 priv->io_base + _REG(VPP_VSC_REGION12_STARTP));
639 writel_relaxed(priv->viu.vpp_vsc_region34_startp,
640 priv->io_base + _REG(VPP_VSC_REGION34_STARTP));
641 writel_relaxed(priv->viu.vpp_vsc_region4_endp,
642 priv->io_base + _REG(VPP_VSC_REGION4_ENDP));
643 writel_relaxed(priv->viu.vpp_vsc_start_phase_step,
644 priv->io_base + _REG(VPP_VSC_START_PHASE_STEP));
645 writel_relaxed(priv->viu.vpp_vsc_ini_phase,
646 priv->io_base + _REG(VPP_VSC_INI_PHASE));
647 writel_relaxed(priv->viu.vpp_vsc_phase_ctrl,
648 priv->io_base + _REG(VPP_VSC_PHASE_CTRL));
649 writel_relaxed(priv->viu.vpp_hsc_phase_ctrl,
650 priv->io_base + _REG(VPP_HSC_PHASE_CTRL));
651 writel_relaxed(0x42, priv->io_base + _REG(VPP_SCALE_COEF_IDX));
655 meson_crtc->enable_vd1(priv);
657 priv->viu.vd1_commit = false;
663 drm_crtc_handle_vblank(priv->crtc);
665 spin_lock_irqsave(&priv->drm->event_lock, flags);
667 drm_crtc_send_vblank_event(priv->crtc, meson_crtc->event);
668 drm_crtc_vblank_put(priv->crtc);
671 spin_unlock_irqrestore(&priv->drm->event_lock, flags);
674 int meson_crtc_create(struct meson_drm *priv)
680 meson_crtc = devm_kzalloc(priv->drm->dev, sizeof(*meson_crtc),
685 meson_crtc->priv = priv;
687 ret = drm_crtc_init_with_planes(priv->drm, crtc,
688 priv->primary_plane, NULL,
691 dev_err(priv->drm->dev, "Failed to init CRTC\n");
695 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
707 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXM)) {
716 priv->crtc = crtc;