Lines Matching refs:dsi
221 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data)
223 u32 temp = readl(dsi->regs + offset);
225 writel((temp & ~mask) | (data & mask), dsi->regs + offset);
228 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi)
231 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, 1000000);
232 struct mtk_phy_timing *timing = &dsi->phy_timing;
260 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0);
261 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1);
262 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2);
263 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3);
266 static void mtk_dsi_enable(struct mtk_dsi *dsi)
268 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, DSI_EN);
271 static void mtk_dsi_disable(struct mtk_dsi *dsi)
273 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_EN, 0);
276 static void mtk_dsi_reset_engine(struct mtk_dsi *dsi)
278 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, DSI_RESET);
279 mtk_dsi_mask(dsi, DSI_CON_CTRL, DSI_RESET, 0);
282 static void mtk_dsi_reset_dphy(struct mtk_dsi *dsi)
284 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, DPHY_RESET);
285 mtk_dsi_mask(dsi, DSI_CON_CTRL, DPHY_RESET, 0);
288 static void mtk_dsi_clk_ulp_mode_enter(struct mtk_dsi *dsi)
290 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
291 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
294 static void mtk_dsi_clk_ulp_mode_leave(struct mtk_dsi *dsi)
296 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_ULPM_EN, 0);
297 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, LC_WAKEUP_EN);
298 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_WAKEUP_EN, 0);
301 static void mtk_dsi_lane0_ulp_mode_enter(struct mtk_dsi *dsi)
303 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_HS_TX_EN, 0);
304 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
307 static void mtk_dsi_lane0_ulp_mode_leave(struct mtk_dsi *dsi)
309 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_ULPM_EN, 0);
310 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, LD0_WAKEUP_EN);
311 mtk_dsi_mask(dsi, DSI_PHY_LD0CON, LD0_WAKEUP_EN, 0);
314 static bool mtk_dsi_clk_hs_state(struct mtk_dsi *dsi)
316 return readl(dsi->regs + DSI_PHY_LCCON) & LC_HS_TX_EN;
319 static void mtk_dsi_clk_hs_mode(struct mtk_dsi *dsi, bool enter)
321 if (enter && !mtk_dsi_clk_hs_state(dsi))
322 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, LC_HS_TX_EN);
323 else if (!enter && mtk_dsi_clk_hs_state(dsi))
324 mtk_dsi_mask(dsi, DSI_PHY_LCCON, LC_HS_TX_EN, 0);
327 static void mtk_dsi_set_mode(struct mtk_dsi *dsi)
331 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
332 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
334 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
340 writel(vid_mode, dsi->regs + DSI_MODE_CTRL);
343 static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi)
345 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, VM_CMD_EN, VM_CMD_EN);
346 mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN);
349 static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi)
351 struct videomode *vm = &dsi->vm;
355 if (dsi->format == MIPI_DSI_FMT_RGB565)
363 switch (dsi->format) {
378 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
379 writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL);
380 writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC);
383 static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi)
387 switch (dsi->lanes) {
405 tmp_reg |= (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) << 6;
406 tmp_reg |= (dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET) >> 3;
408 writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL);
411 static void mtk_dsi_ps_control(struct mtk_dsi *dsi)
416 switch (dsi->format) {
439 tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC;
440 writel(tmp_reg, dsi->regs + DSI_PSCTRL);
443 static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi)
452 struct mtk_phy_timing *timing = &dsi->phy_timing;
454 struct videomode *vm = &dsi->vm;
456 if (dsi->format == MIPI_DSI_FMT_RGB565)
461 writel(vm->vsync_len, dsi->regs + DSI_VSA_NL);
462 writel(vm->vback_porch, dsi->regs + DSI_VBP_NL);
463 writel(vm->vfront_porch, dsi->regs + DSI_VFP_NL);
464 writel(vm->vactive, dsi->regs + DSI_VACT_NL);
466 if (dsi->driver_data->has_size_ctl)
468 dsi->regs + DSI_SIZE_CON);
472 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
481 delta = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? 18 : 12;
485 data_phy_cycles_byte = data_phy_cycles * dsi->lanes + delta;
499 writel(horizontal_sync_active_byte, dsi->regs + DSI_HSA_WC);
500 writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC);
501 writel(horizontal_frontporch_byte, dsi->regs + DSI_HFP_WC);
503 mtk_dsi_ps_control(dsi);
506 static void mtk_dsi_start(struct mtk_dsi *dsi)
508 writel(0, dsi->regs + DSI_START);
509 writel(1, dsi->regs + DSI_START);
512 static void mtk_dsi_stop(struct mtk_dsi *dsi)
514 writel(0, dsi->regs + DSI_START);
517 static void mtk_dsi_set_cmd_mode(struct mtk_dsi *dsi)
519 writel(CMD_MODE, dsi->regs + DSI_MODE_CTRL);
522 static void mtk_dsi_set_interrupt_enable(struct mtk_dsi *dsi)
526 writel(inten, dsi->regs + DSI_INTEN);
529 static void mtk_dsi_irq_data_set(struct mtk_dsi *dsi, u32 irq_bit)
531 dsi->irq_data |= irq_bit;
534 static void mtk_dsi_irq_data_clear(struct mtk_dsi *dsi, u32 irq_bit)
536 dsi->irq_data &= ~irq_bit;
539 static s32 mtk_dsi_wait_for_irq_done(struct mtk_dsi *dsi, u32 irq_flag,
545 ret = wait_event_interruptible_timeout(dsi->irq_wait_queue,
546 dsi->irq_data & irq_flag,
551 mtk_dsi_enable(dsi);
552 mtk_dsi_reset_engine(dsi);
560 struct mtk_dsi *dsi = dev_id;
564 status = readl(dsi->regs + DSI_INTSTA) & flag;
568 mtk_dsi_mask(dsi, DSI_RACK, RACK, RACK);
569 tmp = readl(dsi->regs + DSI_INTSTA);
572 mtk_dsi_mask(dsi, DSI_INTSTA, status, 0);
573 mtk_dsi_irq_data_set(dsi, status);
574 wake_up_interruptible(&dsi->irq_wait_queue);
580 static s32 mtk_dsi_switch_to_cmd_mode(struct mtk_dsi *dsi, u8 irq_flag, u32 t)
582 mtk_dsi_irq_data_clear(dsi, irq_flag);
583 mtk_dsi_set_cmd_mode(dsi);
585 if (!mtk_dsi_wait_for_irq_done(dsi, irq_flag, t)) {
593 static int mtk_dsi_poweron(struct mtk_dsi *dsi)
595 struct device *dev = dsi->host.dev;
599 if (++dsi->refcount != 1)
602 switch (dsi->format) {
616 dsi->data_rate = DIV_ROUND_UP_ULL(dsi->vm.pixelclock * bit_per_pixel,
617 dsi->lanes);
619 ret = clk_set_rate(dsi->hs_clk, dsi->data_rate);
625 phy_power_on(dsi->phy);
627 ret = clk_prepare_enable(dsi->engine_clk);
633 ret = clk_prepare_enable(dsi->digital_clk);
639 mtk_dsi_enable(dsi);
641 if (dsi->driver_data->has_shadow_ctl)
643 dsi->regs + DSI_SHADOW_DEBUG);
645 mtk_dsi_reset_engine(dsi);
646 mtk_dsi_phy_timconfig(dsi);
648 mtk_dsi_ps_control_vact(dsi);
649 mtk_dsi_set_vm_cmd(dsi);
650 mtk_dsi_config_vdo_timing(dsi);
651 mtk_dsi_set_interrupt_enable(dsi);
655 clk_disable_unprepare(dsi->engine_clk);
657 phy_power_off(dsi->phy);
659 dsi->refcount--;
663 static void mtk_dsi_poweroff(struct mtk_dsi *dsi)
665 if (WARN_ON(dsi->refcount == 0))
668 if (--dsi->refcount != 0)
676 * after dsi is fully set.
678 mtk_dsi_stop(dsi);
680 mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
681 mtk_dsi_reset_engine(dsi);
682 mtk_dsi_lane0_ulp_mode_enter(dsi);
683 mtk_dsi_clk_ulp_mode_enter(dsi);
685 writel(0, dsi->regs + DSI_TXRX_CTRL);
687 mtk_dsi_disable(dsi);
689 clk_disable_unprepare(dsi->engine_clk);
690 clk_disable_unprepare(dsi->digital_clk);
692 phy_power_off(dsi->phy);
694 dsi->lanes_ready = false;
697 static void mtk_dsi_lane_ready(struct mtk_dsi *dsi)
699 if (!dsi->lanes_ready) {
700 dsi->lanes_ready = true;
701 mtk_dsi_rxtx_control(dsi);
703 mtk_dsi_reset_dphy(dsi);
704 mtk_dsi_clk_ulp_mode_leave(dsi);
705 mtk_dsi_lane0_ulp_mode_leave(dsi);
706 mtk_dsi_clk_hs_mode(dsi, 0);
712 static void mtk_output_dsi_enable(struct mtk_dsi *dsi)
714 if (dsi->enabled)
717 mtk_dsi_lane_ready(dsi);
718 mtk_dsi_set_mode(dsi);
719 mtk_dsi_clk_hs_mode(dsi, 1);
721 mtk_dsi_start(dsi);
723 dsi->enabled = true;
726 static void mtk_output_dsi_disable(struct mtk_dsi *dsi)
728 if (!dsi->enabled)
731 dsi->enabled = false;
737 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
739 /* Attach the panel or bridge to the dsi bridge */
740 return drm_bridge_attach(bridge->encoder, dsi->next_bridge,
741 &dsi->bridge, flags);
748 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
750 drm_display_mode_to_videomode(adjusted, &dsi->vm);
756 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
758 mtk_output_dsi_disable(dsi);
764 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
766 if (dsi->refcount == 0)
769 mtk_output_dsi_enable(dsi);
775 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
778 ret = mtk_dsi_poweron(dsi);
780 DRM_ERROR("failed to power on dsi\n");
786 struct mtk_dsi *dsi = bridge_to_dsi(bridge);
788 mtk_dsi_poweroff(dsi);
805 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
807 mtk_dsi_poweron(dsi);
812 struct mtk_dsi *dsi = container_of(comp, struct mtk_dsi, ddp_comp);
814 mtk_dsi_poweroff(dsi);
825 struct mtk_dsi *dsi = host_to_dsi(host);
827 dsi->lanes = device->lanes;
828 dsi->format = device->format;
829 dsi->mode_flags = device->mode_flags;
834 static void mtk_dsi_wait_for_idle(struct mtk_dsi *dsi)
839 ret = readl_poll_timeout(dsi->regs + DSI_INTSTA, val, !(val & DSI_BUSY),
842 DRM_WARN("polling dsi wait not busy timeout!\n");
844 mtk_dsi_enable(dsi);
845 mtk_dsi_reset_engine(dsi);
872 static void mtk_dsi_cmdq(struct mtk_dsi *dsi, const struct mipi_dsi_msg *msg)
877 u32 reg_cmdq_off = dsi->driver_data->reg_cmdq_off;
897 mtk_dsi_mask(dsi, (reg_cmdq_off + cmdq_off + i) & (~0x3U),
901 mtk_dsi_mask(dsi, reg_cmdq_off, cmdq_mask, reg_val);
902 mtk_dsi_mask(dsi, DSI_CMDQ_SIZE, CMDQ_SIZE, cmdq_size);
905 static ssize_t mtk_dsi_host_send_cmd(struct mtk_dsi *dsi,
908 mtk_dsi_wait_for_idle(dsi);
909 mtk_dsi_irq_data_clear(dsi, flag);
910 mtk_dsi_cmdq(dsi, msg);
911 mtk_dsi_start(dsi);
913 if (!mtk_dsi_wait_for_irq_done(dsi, flag, 2000))
922 struct mtk_dsi *dsi = host_to_dsi(host);
930 dsi_mode = readl(dsi->regs + DSI_MODE_CTRL);
932 mtk_dsi_stop(dsi);
933 ret = mtk_dsi_switch_to_cmd_mode(dsi, VM_DONE_INT_FLAG, 500);
941 mtk_dsi_lane_ready(dsi);
943 ret = mtk_dsi_host_send_cmd(dsi, msg, irq_flag);
953 DRM_ERROR("dsi receive buffer size may be NULL\n");
959 *(read_data + i) = readb(dsi->regs + DSI_RX_DATA0 + i);
977 DRM_INFO("dsi get %d byte data from the panel address(0x%x)\n",
982 mtk_dsi_set_mode(dsi);
983 mtk_dsi_start(dsi);
994 static int mtk_dsi_encoder_init(struct drm_device *drm, struct mtk_dsi *dsi)
998 ret = drm_simple_encoder_init(drm, &dsi->encoder,
1005 dsi->encoder.possible_crtcs = mtk_drm_find_possible_crtc_by_comp(drm, dsi->ddp_comp);
1007 ret = drm_bridge_attach(&dsi->encoder, &dsi->bridge, NULL,
1012 dsi->connector = drm_bridge_connector_init(drm, &dsi->encoder);
1013 if (IS_ERR(dsi->connector)) {
1015 ret = PTR_ERR(dsi->connector);
1018 drm_connector_attach_encoder(dsi->connector, &dsi->encoder);
1023 drm_encoder_cleanup(&dsi->encoder);
1031 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1033 ret = mtk_ddp_comp_register(drm, &dsi->ddp_comp);
1040 ret = mtk_dsi_encoder_init(drm, dsi);
1047 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1055 struct mtk_dsi *dsi = dev_get_drvdata(dev);
1057 drm_encoder_cleanup(&dsi->encoder);
1058 mtk_ddp_comp_unregister(drm, &dsi->ddp_comp);
1068 struct mtk_dsi *dsi;
1076 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL);
1077 if (!dsi)
1080 dsi->host.ops = &mtk_dsi_ops;
1081 dsi->host.dev = dev;
1082 ret = mipi_dsi_host_register(&dsi->host);
1089 &panel, &dsi->next_bridge);
1094 dsi->next_bridge = devm_drm_panel_bridge_add(dev, panel);
1095 if (IS_ERR(dsi->next_bridge)) {
1096 ret = PTR_ERR(dsi->next_bridge);
1101 dsi->driver_data = of_device_get_match_data(dev);
1103 dsi->engine_clk = devm_clk_get(dev, "engine");
1104 if (IS_ERR(dsi->engine_clk)) {
1105 ret = PTR_ERR(dsi->engine_clk);
1112 dsi->digital_clk = devm_clk_get(dev, "digital");
1113 if (IS_ERR(dsi->digital_clk)) {
1114 ret = PTR_ERR(dsi->digital_clk);
1121 dsi->hs_clk = devm_clk_get(dev, "hs");
1122 if (IS_ERR(dsi->hs_clk)) {
1123 ret = PTR_ERR(dsi->hs_clk);
1129 dsi->regs = devm_ioremap_resource(dev, regs);
1130 if (IS_ERR(dsi->regs)) {
1131 ret = PTR_ERR(dsi->regs);
1136 dsi->phy = devm_phy_get(dev, "dphy");
1137 if (IS_ERR(dsi->phy)) {
1138 ret = PTR_ERR(dsi->phy);
1150 ret = mtk_ddp_comp_init(dev, dev->of_node, &dsi->ddp_comp, comp_id,
1159 dev_err(&pdev->dev, "failed to get dsi irq_num: %d\n", irq_num);
1166 IRQF_TRIGGER_LOW, dev_name(&pdev->dev), dsi);
1168 dev_err(&pdev->dev, "failed to request mediatek dsi irq\n");
1172 init_waitqueue_head(&dsi->irq_wait_queue);
1174 platform_set_drvdata(pdev, dsi);
1176 dsi->bridge.funcs = &mtk_dsi_bridge_funcs;
1177 dsi->bridge.of_node = dev->of_node;
1178 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
1180 drm_bridge_add(&dsi->bridge);
1191 mipi_dsi_host_unregister(&dsi->host);
1197 struct mtk_dsi *dsi = platform_get_drvdata(pdev);
1199 mtk_output_dsi_disable(dsi);
1200 drm_bridge_remove(&dsi->bridge);
1202 mipi_dsi_host_unregister(&dsi->host);
1222 { .compatible = "mediatek,mt2701-dsi",
1224 { .compatible = "mediatek,mt8173-dsi",
1226 { .compatible = "mediatek,mt8183-dsi",
1235 .name = "mtk-dsi",