Lines Matching refs:cec
59 static void mtk_cec_clear_bits(struct mtk_cec *cec, unsigned int offset,
62 void __iomem *reg = cec->regs + offset;
70 static void mtk_cec_set_bits(struct mtk_cec *cec, unsigned int offset,
73 void __iomem *reg = cec->regs + offset;
81 static void mtk_cec_mask(struct mtk_cec *cec, unsigned int offset,
84 u32 tmp = readl(cec->regs + offset) & ~mask;
87 writel(tmp, cec->regs + offset);
94 struct mtk_cec *cec = dev_get_drvdata(dev);
97 spin_lock_irqsave(&cec->lock, flags);
98 cec->hdmi_dev = hdmi_dev;
99 cec->hpd_event = hpd_event;
100 spin_unlock_irqrestore(&cec->lock, flags);
105 struct mtk_cec *cec = dev_get_drvdata(dev);
108 status = readl(cec->regs + RX_EVENT);
113 static void mtk_cec_htplg_irq_init(struct mtk_cec *cec)
115 mtk_cec_mask(cec, CEC_CKGEN, 0 | CEC_32K_PDN, PDN | CEC_32K_PDN);
116 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
118 mtk_cec_mask(cec, RX_GEN_WD, 0, HDMI_PORD_INT_32K_CLR | RX_INT_32K_CLR |
123 static void mtk_cec_htplg_irq_enable(struct mtk_cec *cec)
125 mtk_cec_set_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
128 static void mtk_cec_htplg_irq_disable(struct mtk_cec *cec)
130 mtk_cec_clear_bits(cec, RX_EVENT, HDMI_PORD_INT_EN | HDMI_HTPLG_INT_EN);
133 static void mtk_cec_clear_htplg_irq(struct mtk_cec *cec)
135 mtk_cec_set_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
136 mtk_cec_set_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
138 mtk_cec_set_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
141 mtk_cec_clear_bits(cec, NORMAL_INT_CTRL, HDMI_HTPLG_INT_CLR |
143 mtk_cec_clear_bits(cec, TR_CONFIG, CLEAR_CEC_IRQ);
144 mtk_cec_clear_bits(cec, RX_GEN_WD, HDMI_PORD_INT_32K_CLR |
148 static void mtk_cec_hpd_event(struct mtk_cec *cec, bool hpd)
154 spin_lock_irqsave(&cec->lock, flags);
155 hpd_event = cec->hpd_event;
156 hdmi_dev = cec->hdmi_dev;
157 spin_unlock_irqrestore(&cec->lock, flags);
166 struct mtk_cec *cec = dev_get_drvdata(dev);
169 mtk_cec_clear_htplg_irq(cec);
172 if (cec->hpd != hpd) {
174 cec->hpd, hpd);
175 cec->hpd = hpd;
176 mtk_cec_hpd_event(cec, hpd);
184 struct mtk_cec *cec;
188 cec = devm_kzalloc(dev, sizeof(*cec), GFP_KERNEL);
189 if (!cec)
192 platform_set_drvdata(pdev, cec);
193 spin_lock_init(&cec->lock);
196 cec->regs = devm_ioremap_resource(dev, res);
197 if (IS_ERR(cec->regs)) {
198 ret = PTR_ERR(cec->regs);
199 dev_err(dev, "Failed to ioremap cec: %d\n", ret);
203 cec->clk = devm_clk_get(dev, NULL);
204 if (IS_ERR(cec->clk)) {
205 ret = PTR_ERR(cec->clk);
206 dev_err(dev, "Failed to get cec clock: %d\n", ret);
210 cec->irq = platform_get_irq(pdev, 0);
211 if (cec->irq < 0) {
212 dev_err(dev, "Failed to get cec irq: %d\n", cec->irq);
213 return cec->irq;
216 ret = devm_request_threaded_irq(dev, cec->irq, NULL,
221 dev_err(dev, "Failed to register cec irq: %d\n", ret);
225 ret = clk_prepare_enable(cec->clk);
227 dev_err(dev, "Failed to enable cec clock: %d\n", ret);
231 mtk_cec_htplg_irq_init(cec);
232 mtk_cec_htplg_irq_enable(cec);
239 struct mtk_cec *cec = platform_get_drvdata(pdev);
241 mtk_cec_htplg_irq_disable(cec);
242 clk_disable_unprepare(cec->clk);
247 { .compatible = "mediatek,mt8173-cec", },
255 .name = "mediatek-cec",