Lines Matching refs:sync
491 u32 sync;
499 sync = MCDE_CHNL0SYNCHMOD;
506 sync = MCDE_CHNL1SYNCHMOD;
513 sync = MCDE_CHNL2SYNCHMOD;
520 sync = MCDE_CHNL3SYNCHMOD;
527 /* Set up channel 0 sync (based on chnl_update_registers()) */
530 /* Oneshot is achieved with software sync */
545 * The vendor driver uses the formatter as sync source
570 writel(val, mcde->regs + sync);
652 u32 sync;
661 sync = MCDE_DSIVID0SYNC;
670 sync = MCDE_DSIVID1SYNC;
679 sync = MCDE_DSIVID2SYNC;
718 writel(0, mcde->regs + sync);
841 /* Trigger a software sync out on respective channel (0-3) */
1110 /* Trigger a software sync out on channel 0 */
1115 * Disable FIFO A flow again: since we are using TE sync we