Lines Matching refs:mcde
66 void mcde_display_irq(struct mcde *mcde)
72 mispp = readl(mcde->regs + MCDE_MISPP);
73 misovl = readl(mcde->regs + MCDE_MISOVL);
74 mischnl = readl(mcde->regs + MCDE_MISCHNL);
84 if (mcde_dsi_irq(mcde->mdsi)) {
93 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
94 spin_lock(&mcde->flow_lock);
95 if (--mcde->flow_active == 0) {
96 dev_dbg(mcde->dev, "TE0 IRQ\n");
98 val = readl(mcde->regs + MCDE_CRA0);
100 writel(val, mcde->regs + MCDE_CRA0);
102 spin_unlock(&mcde->flow_lock);
108 dev_dbg(mcde->dev, "chnl A vblank IRQ\n");
112 dev_dbg(mcde->dev, "chnl B vblank IRQ\n");
116 dev_dbg(mcde->dev, "chnl C0 vblank IRQ\n");
118 dev_dbg(mcde->dev, "chnl C1 vblank IRQ\n");
120 dev_dbg(mcde->dev, "chnl C0 TE IRQ\n");
122 dev_dbg(mcde->dev, "chnl C1 TE IRQ\n");
123 writel(mispp, mcde->regs + MCDE_RISPP);
126 drm_crtc_handle_vblank(&mcde->pipe.crtc);
129 dev_info(mcde->dev, "some stray overlay IRQ %08x\n", misovl);
130 writel(misovl, mcde->regs + MCDE_RISOVL);
133 dev_info(mcde->dev, "some stray channel error IRQ %08x\n",
135 writel(mischnl, mcde->regs + MCDE_RISCHNL);
138 void mcde_display_disable_irqs(struct mcde *mcde)
141 writel(0, mcde->regs + MCDE_IMSCPP);
142 writel(0, mcde->regs + MCDE_IMSCOVL);
143 writel(0, mcde->regs + MCDE_IMSCCHNL);
146 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
147 writel(0xFFFFFFFF, mcde->regs + MCDE_RISOVL);
148 writel(0xFFFFFFFF, mcde->regs + MCDE_RISCHNL);
188 static int mcde_configure_extsrc(struct mcde *mcde, enum mcde_extsrc src,
319 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
323 writel(val, mcde->regs + conf);
328 writel(val, mcde->regs + cr);
333 static void mcde_configure_overlay(struct mcde *mcde, enum mcde_overlay ovl,
403 writel(val, mcde->regs + conf1);
427 dev_err(mcde->dev, "Unknown pixel format 0x%08x\n",
455 dev_dbg(mcde->dev, "pixel fetcher watermark level %d pixels\n",
458 writel(val, mcde->regs + conf2);
461 writel(mcde->stride, mcde->regs + ljinc);
463 writel(0, mcde->regs + crop);
475 writel(val, mcde->regs + cr);
482 writel(val, mcde->regs + comp);
485 static void mcde_configure_channel(struct mcde *mcde, enum mcde_channel ch,
528 switch (mcde->flow_mode) {
565 dev_err(mcde->dev, "unknown flow mode %d\n",
566 mcde->flow_mode);
570 writel(val, mcde->regs + sync);
575 writel(val, mcde->regs + conf);
583 writel(val, mcde->regs + stat);
584 writel(0, mcde->regs + bgcol);
590 mcde->regs + mux);
594 mcde->regs + mux);
599 static void mcde_configure_fifo(struct mcde *mcde, enum mcde_fifo fifo,
627 writel(val, mcde->regs + ctrl);
632 writel(val, mcde->regs + cr0);
640 writel(val, mcde->regs + cr1);
643 static void mcde_configure_dsi_formatter(struct mcde *mcde,
691 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO)
693 switch (mcde->mdsi->format) {
711 dev_err(mcde->dev, "unknown DSI format\n");
714 writel(val, mcde->regs + conf0);
716 writel(formatter_frame, mcde->regs + frame);
717 writel(pkt_size, mcde->regs + pkt);
718 writel(0, mcde->regs + sync);
724 writel(val, mcde->regs + cmdw);
730 writel(0, mcde->regs + delay0);
731 writel(0, mcde->regs + delay1);
734 static void mcde_enable_fifo(struct mcde *mcde, enum mcde_fifo fifo)
747 dev_err(mcde->dev, "cannot enable FIFO %c\n",
752 spin_lock(&mcde->flow_lock);
753 val = readl(mcde->regs + cr);
755 writel(val, mcde->regs + cr);
756 mcde->flow_active++;
757 spin_unlock(&mcde->flow_lock);
760 static void mcde_disable_fifo(struct mcde *mcde, enum mcde_fifo fifo,
775 dev_err(mcde->dev, "cannot disable FIFO %c\n",
780 spin_lock(&mcde->flow_lock);
781 val = readl(mcde->regs + cr);
783 writel(val, mcde->regs + cr);
784 mcde->flow_active = 0;
785 spin_unlock(&mcde->flow_lock);
791 while (readl(mcde->regs + cr) & MCDE_CRX0_FLOEN) {
794 dev_err(mcde->dev,
805 static void mcde_drain_pipe(struct mcde *mcde, enum mcde_fifo fifo,
836 val = readl(mcde->regs + ctrl);
838 dev_err(mcde->dev, "Channel A FIFO not empty (handover)\n");
840 mcde_enable_fifo(mcde, fifo);
842 writel(MCDE_CHNLXSYNCHSW_SW_TRIG, mcde->regs + synsw);
844 mcde_disable_fifo(mcde, fifo, true);
870 struct mcde *mcde = to_mcde(drm);
886 ret = regulator_enable(mcde->epod);
895 if (!mcde->mdsi) {
914 writel(val, mcde->regs + MCDE_CONF0);
917 mcde_display_disable_irqs(mcde);
918 writel(0, mcde->regs + MCDE_IMSCERR);
919 writel(0xFFFFFFFF, mcde->regs + MCDE_RISERR);
922 (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) ?
924 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format));
926 mipi_dsi_pixel_format_to_bpp(mcde->mdsi->format) / 8;
943 if (mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
958 if (!(mcde->mdsi->mode_flags & MIPI_DSI_MODE_VIDEO))
965 mcde->stride = mode->hdisplay * cpp;
967 mcde->stride);
973 mcde_drain_pipe(mcde, MCDE_FIFO_A, MCDE_CHANNEL_0);
982 mcde_configure_extsrc(mcde, MCDE_EXTSRC_0, format);
989 mcde_configure_overlay(mcde, MCDE_OVERLAY_0, MCDE_EXTSRC_0,
996 mcde_configure_channel(mcde, MCDE_CHANNEL_0, MCDE_FIFO_A, mode);
999 mcde_configure_fifo(mcde, MCDE_FIFO_A, MCDE_DSI_FORMATTER_0,
1010 mcde_dsi_enable(mcde->bridge);
1013 mcde_configure_dsi_formatter(mcde, MCDE_DSI_FORMATTER_0,
1016 switch (mcde->flow_mode) {
1025 writel(val, mcde->regs + MCDE_VSCRC0);
1027 val = readl(mcde->regs + MCDE_CRC);
1029 writel(val, mcde->regs + MCDE_CRC);
1046 if (mcde->flow_mode != MCDE_COMMAND_ONESHOT_FLOW) {
1047 mcde_enable_fifo(mcde, MCDE_FIFO_A);
1048 dev_dbg(mcde->dev, "started MCDE video FIFO flow\n");
1052 val = readl(mcde->regs + MCDE_CR);
1054 writel(val, mcde->regs + MCDE_CR);
1063 struct mcde *mcde = to_mcde(drm);
1070 mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
1073 mcde_dsi_disable(mcde->bridge);
1084 ret = regulator_disable(mcde->epod);
1093 static void mcde_start_flow(struct mcde *mcde)
1096 if (mcde->flow_mode == MCDE_COMMAND_BTA_TE_FLOW)
1097 mcde_dsi_te_request(mcde->mdsi);
1100 mcde_enable_fifo(mcde, MCDE_FIFO_A);
1109 if (mcde->flow_mode == MCDE_COMMAND_ONESHOT_FLOW) {
1112 mcde->regs + MCDE_CHNL0SYNCHSW);
1121 mcde_disable_fifo(mcde, MCDE_FIFO_A, true);
1124 dev_dbg(mcde->dev, "started MCDE FIFO flow\n");
1127 static void mcde_set_extsrc(struct mcde *mcde, u32 buffer_address)
1130 writel(buffer_address, mcde->regs + MCDE_EXTSRCXA0);
1135 writel(buffer_address + mcde->stride, mcde->regs + MCDE_EXTSRCXA1);
1143 struct mcde *mcde = to_mcde(drm);
1166 dev_dbg(mcde->dev, "arm vblank event\n");
1169 dev_dbg(mcde->dev, "insert fake vblank event\n");
1182 mcde_set_extsrc(mcde, drm_fb_cma_get_gem_addr(fb, pstate, 0));
1183 dev_info_once(mcde->dev, "first update of display contents\n");
1188 if (mcde->flow_active == 0)
1189 mcde_start_flow(mcde);
1196 dev_info(mcde->dev, "ignored a display update\n");
1204 struct mcde *mcde = to_mcde(drm);
1214 writel(val, mcde->regs + MCDE_IMSCPP);
1223 struct mcde *mcde = to_mcde(drm);
1226 writel(0, mcde->regs + MCDE_IMSCPP);
1228 writel(0xFFFFFFFF, mcde->regs + MCDE_RISPP);
1243 struct mcde *mcde = to_mcde(drm);
1264 ret = drm_simple_display_pipe_init(drm, &mcde->pipe,
1268 mcde->connector);