Lines Matching refs:lcrtc
33 struct loongson_crtc *lcrtc = to_loongson_crtc(crtc);
34 struct loongson_drm_device *ldev = lcrtc->ldev;
36 if(lcrtc->crtc_id == 0) {
51 struct loongson_crtc *lcrtc = to_loongson_crtc(crtc);
52 struct loongson_drm_device *ldev = lcrtc->ldev;
55 if(lcrtc->crtc_id == 0) {
258 u32 crtc_read(struct loongson_crtc *lcrtc, u32 offset)
260 struct loongson_drm_device *ldev = lcrtc->ldev;
261 return readl(ldev->mmio + offset + (lcrtc->crtc_id * CRTC_REG_OFFSET));
264 void crtc_write(struct loongson_crtc *lcrtc, u32 offset, u32 val)
266 struct loongson_drm_device *ldev = lcrtc->ldev;
267 writel(val, ldev->mmio + offset + (lcrtc->crtc_id * CRTC_REG_OFFSET));
276 struct loongson_crtc *lcrtc = to_loongson_crtc(crtc);
292 lcrtc->crtc_id, hr, hss, hse, hfl, vr, vss, vse, vfl, pix_freq);
295 crtc_write(lcrtc, FB_DITCFG_DVO_REG, 0);
296 crtc_write(lcrtc, FB_DITTAB_LO_DVO_REG, 0);
297 crtc_write(lcrtc, FB_DITTAB_HI_DVO_REG, 0);
298 crtc_write(lcrtc, FB_PANCFG_DVO_REG, 0x80001311);
299 crtc_write(lcrtc, FB_PANTIM_DVO_REG, 0);
301 crtc_write(lcrtc, FB_HDISPLAY_DVO_REG, (mode->crtc_htotal << 16) | mode->crtc_hdisplay);
302 crtc_write(lcrtc, FB_HSYNC_DVO_REG, 0x40000000 | (mode->crtc_hsync_end << 16) | mode->crtc_hsync_start);
304 crtc_write(lcrtc, FB_VDISPLAY_DVO_REG, (mode->crtc_vtotal << 16) | mode->crtc_vdisplay);
305 crtc_write(lcrtc, FB_VSYNC_DVO_REG, 0x40000000 | (mode->crtc_vsync_end << 16) | mode->crtc_vsync_start);
307 crtc_write(lcrtc, FB_STRI_DVO_REG, (crtc->primary->state->fb->pitches[0] + 255) & ~255);
313 lcrtc->cfg_reg |= 0x3;
314 crtc_write(lcrtc, FB_CFG_DVO_REG, lcrtc->cfg_reg);
318 lcrtc->cfg_reg |= 0x4;
319 crtc_write(lcrtc, FB_CFG_DVO_REG, lcrtc->cfg_reg);
324 loongson_config_pll(lcrtc->crtc_id, mode->clock);
331 struct loongson_crtc *lcrtc = to_loongson_crtc(crtc);
333 if (lcrtc->cfg_reg & CFG_ENABLE)
336 lcrtc->cfg_reg |= CFG_ENABLE;
338 crtc_write(lcrtc, FB_CFG_DVO_REG, lcrtc->cfg_reg);
349 struct loongson_crtc *lcrtc = to_loongson_crtc(crtc);
351 lcrtc->cfg_reg &= ~CFG_ENABLE;
353 crtc_write(lcrtc, FB_CFG_DVO_REG, lcrtc->cfg_reg);
389 struct loongson_crtc *lcrtc;
397 lcrtc = to_loongson_crtc(state->crtc);
398 ldev = lcrtc->ldev;
399 id = lcrtc->crtc_id;
404 ldev->lcrtc[1].cfg_reg |= CFG_PANELSWITCH;
406 ldev->lcrtc[1].cfg_reg &= ~CFG_PANELSWITCH;
409 crtc_write(lcrtc, FB_STRI_DVO_REG, (pitch + 255) & ~255);
410 if (crtc_read(lcrtc, FB_CFG_DVO_REG) & CFG_FBNUM)
411 crtc_write(lcrtc, FB_ADDR0_DVO_REG, drm_fb_cma_get_gem_addr(state->fb, state, 0));
413 crtc_write(lcrtc, FB_ADDR1_DVO_REG, drm_fb_cma_get_gem_addr(state->fb, state, 0));
415 lcrtc->cfg_reg |= CFG_ENABLE;
416 crtc_write(lcrtc, FB_CFG_DVO_REG, lcrtc->cfg_reg | CFG_FBSWITCH);
419 crtc_write(&ldev->lcrtc[0], FB_CFG_DVO_REG, ldev->lcrtc[0].cfg_reg | CFG_ENABLE);
421 crtc_write(&ldev->lcrtc[1], FB_CFG_DVO_REG, ldev->lcrtc[1].cfg_reg | CFG_ENABLE);
479 ldev->lcrtc[i].ldev = ldev;
480 ldev->lcrtc[i].crtc_id = i;
482 ldev->lcrtc[i].cfg_reg = CFG_RESET;
483 ldev->lcrtc[i].primary = devm_kzalloc(ldev->dev->dev, sizeof(*ldev->lcrtc[i].primary), GFP_KERNEL);
484 if (!ldev->lcrtc[i].primary)
487 ret = drm_universal_plane_init(ldev->dev, ldev->lcrtc[i].primary, BIT(i), &loongson_plane_funcs,
493 drm_plane_helper_add(ldev->lcrtc[i].primary, &loongson_plane_helper_funcs);
496 ret = drm_crtc_init_with_planes(ldev->dev, &ldev->lcrtc[i].base,ldev->lcrtc[i].primary,
499 ret = drm_crtc_init_with_planes(ldev->dev, &ldev->lcrtc[i].base,ldev->lcrtc[i].primary,
502 loongson_plane_destroy(ldev->lcrtc[i].primary);
505 drm_crtc_helper_add(&ldev->lcrtc[i].base, &loongson_crtc_helper_funcs);