Lines Matching refs:ipu
9 #include "ingenic-ipu.h"
40 void (*set_coefs)(struct ingenic_ipu *ipu, unsigned int reg,
116 static void jz4760_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
160 regmap_write(ipu->map, reg, val);
165 regmap_write(ipu->map, reg, val);
168 static void jz4725b_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
184 regmap_write(ipu->map, reg, val);
188 regmap_write(ipu->map, reg, JZ4725B_IPU_RSZ_LUT_IN_EN);
192 static void ingenic_ipu_set_downscale_coefs(struct ingenic_ipu *ipu,
205 ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
210 static void ingenic_ipu_set_integer_upscale_coefs(struct ingenic_ipu *ipu,
221 ipu->soc_info->set_coefs(ipu, reg, 0, false, 512, i == num - 1);
224 static void ingenic_ipu_set_upscale_coefs(struct ingenic_ipu *ipu,
239 ipu->soc_info->set_coefs(ipu, reg, ipu->sharpness,
244 static void ingenic_ipu_set_coefs(struct ingenic_ipu *ipu, unsigned int reg,
248 regmap_write(ipu->map, reg, -1);
251 ingenic_ipu_set_downscale_coefs(ipu, reg, num, denom);
253 ingenic_ipu_set_integer_upscale_coefs(ipu, reg, num);
255 ingenic_ipu_set_upscale_coefs(ipu, reg, num, denom);
287 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
299 if (!ipu->clk_enabled) {
300 err = clk_enable(ipu->clk);
302 dev_err(ipu->dev, "Unable to enable clock: %d\n", err);
306 ipu->clk_enabled = true;
312 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RST);
315 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
320 ipu->addr_y = drm_fb_cma_get_gem_addr(state->fb, state, 0);
322 ipu->addr_u = drm_fb_cma_get_gem_addr(state->fb, state, 1);
324 ipu->addr_v = drm_fb_cma_get_gem_addr(state->fb, state, 2);
330 regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
331 regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
332 regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
335 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_SPKG_SEL);
337 ingenic_drm_plane_config(ipu->master, plane, DRM_FORMAT_XRGB8888);
348 regmap_write(ipu->map, JZ_REG_IPU_UV_STRIDE, stride);
351 regmap_write(ipu->map, JZ_REG_IPU_Y_STRIDE, stride);
353 regmap_write(ipu->map, JZ_REG_IPU_IN_GS,
420 regmap_write(ipu->map, JZ_REG_IPU_D_FMT, format);
423 regmap_write(ipu->map, JZ_REG_IPU_OUT_GS,
426 regmap_write(ipu->map, JZ_REG_IPU_OUT_STRIDE, state->crtc_w * 4);
429 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CSC_EN);
437 regmap_write(ipu->map, JZ_REG_IPU_CSC_OFFSET,
447 regmap_write(ipu->map, JZ_REG_IPU_CSC_C0_COEF, 0x4a8);
448 regmap_write(ipu->map, JZ_REG_IPU_CSC_C1_COEF, 0x662);
449 regmap_write(ipu->map, JZ_REG_IPU_CSC_C2_COEF, 0x191);
450 regmap_write(ipu->map, JZ_REG_IPU_CSC_C3_COEF, 0x341);
451 regmap_write(ipu->map, JZ_REG_IPU_CSC_C4_COEF, 0x811);
461 if (ipu->soc_info->has_bicubic)
464 upscaling_w = ipu->num_w > ipu->denom_w;
468 if (ipu->num_w != 1 || ipu->denom_w != 1) {
469 if (!ipu->soc_info->has_bicubic && !upscaling_w)
470 coef_index |= (ipu->denom_w - 1) << 16;
472 coef_index |= (ipu->num_w - 1) << 16;
476 upscaling_h = ipu->num_h > ipu->denom_h;
480 if (ipu->num_h != 1 || ipu->denom_h != 1) {
481 if (!ipu->soc_info->has_bicubic && !upscaling_h)
482 coef_index |= ipu->denom_h - 1;
484 coef_index |= ipu->num_h - 1;
488 regmap_update_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_ZOOM_SEL |
493 regmap_write(ipu->map, JZ_REG_IPU_RSZ_COEF_INDEX, coef_index);
495 if (ipu->num_w != 1 || ipu->denom_w != 1)
496 ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_HRSZ_COEF_LUT,
497 ipu->num_w, ipu->denom_w);
499 if (ipu->num_h != 1 || ipu->denom_h != 1)
500 ingenic_ipu_set_coefs(ipu, JZ_REG_IPU_VRSZ_COEF_LUT,
501 ipu->num_h, ipu->denom_h);
504 regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
507 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL,
510 dev_dbg(ipu->dev, "Scaling %ux%u to %ux%u (%u:%u horiz, %u:%u vert)\n",
513 ipu->num_w, ipu->denom_w, ipu->num_h, ipu->denom_h);
520 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
576 ipu->num_w = num_w;
577 ipu->num_h = num_h;
578 ipu->denom_w = denom_w;
579 ipu->denom_h = denom_h;
587 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
589 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_STOP);
590 regmap_clear_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_CHIP_EN);
592 ingenic_drm_plane_disable(ipu->master, plane);
594 if (ipu->clk_enabled) {
595 clk_disable(ipu->clk);
596 ipu->clk_enabled = false;
612 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
614 if (property != ipu->sharpness_prop)
617 *val = ipu->sharpness;
627 struct ingenic_ipu *ipu = plane_to_ingenic_ipu(plane);
630 if (property != ipu->sharpness_prop)
633 ipu->sharpness = val;
661 struct ingenic_ipu *ipu = arg;
662 struct drm_crtc *crtc = drm_crtc_from_index(ipu->drm, 0);
666 if (ipu->soc_info->manual_restart)
667 regmap_read(ipu->map, JZ_REG_IPU_STATUS, &dummy);
670 regmap_write(ipu->map, JZ_REG_IPU_STATUS, 0);
673 regmap_write(ipu->map, JZ_REG_IPU_Y_ADDR, ipu->addr_y);
674 regmap_write(ipu->map, JZ_REG_IPU_U_ADDR, ipu->addr_u);
675 regmap_write(ipu->map, JZ_REG_IPU_V_ADDR, ipu->addr_v);
678 if (ipu->soc_info->manual_restart)
679 regmap_set_bits(ipu->map, JZ_REG_IPU_CTRL, JZ_IPU_CTRL_RUN);
700 struct ingenic_ipu *ipu;
705 ipu = devm_kzalloc(dev, sizeof(*ipu), GFP_KERNEL);
706 if (!ipu)
715 ipu->dev = dev;
716 ipu->drm = drm;
717 ipu->master = master;
718 ipu->soc_info = soc_info;
726 ipu->map = devm_regmap_init_mmio(dev, base, &ingenic_ipu_regmap_config);
727 if (IS_ERR(ipu->map)) {
729 return PTR_ERR(ipu->map);
736 ipu->clk = devm_clk_get(dev, "ipu");
737 if (IS_ERR(ipu->clk)) {
739 return PTR_ERR(ipu->clk);
743 dev_name(dev), ipu);
749 plane = &ipu->plane;
769 ipu->sharpness_prop = drm_property_create_range(drm, 0, "sharpness",
771 if (!ipu->sharpness_prop) {
777 ipu->sharpness = soc_info->has_bicubic ? 8 : 1;
778 drm_object_attach_property(&plane->base, ipu->sharpness_prop,
779 ipu->sharpness);
781 err = clk_prepare(ipu->clk);
793 struct ingenic_ipu *ipu = dev_get_drvdata(dev);
795 clk_unprepare(ipu->clk);
866 { .compatible = "ingenic,jz4725b-ipu", .data = &jz4725b_soc_info },
867 { .compatible = "ingenic,jz4760-ipu", .data = &jz4760_soc_info },
874 .name = "ingenic-ipu",