Lines Matching refs:dtg
98 static void dcss_dtg_write(struct dcss_dtg *dtg, u32 val, u32 ofs)
100 if (!dtg->in_use)
101 dcss_writel(val, dtg->base_reg + ofs);
103 dcss_ctxld_write(dtg->ctxld, dtg->ctx_id,
104 val, dtg->base_ofs + ofs);
109 struct dcss_dtg *dtg = data;
112 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
117 dcss_ctxld_kick(dtg->ctxld);
119 dcss_writel(status & LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);
124 static int dcss_dtg_irq_config(struct dcss_dtg *dtg,
129 dtg->ctxld_kick_irq = platform_get_irq_byname(pdev, "ctxld_kick");
130 if (dtg->ctxld_kick_irq < 0)
131 return dtg->ctxld_kick_irq;
134 dtg->base_reg + DCSS_DTG_INT_MASK);
136 ret = request_irq(dtg->ctxld_kick_irq, dcss_dtg_irq_handler,
137 0, "dcss_ctxld_kick", dtg);
139 dev_err(dtg->dev, "dtg: irq request failed.\n");
143 disable_irq(dtg->ctxld_kick_irq);
145 dtg->ctxld_kick_irq_en = false;
153 struct dcss_dtg *dtg;
155 dtg = kzalloc(sizeof(*dtg), GFP_KERNEL);
156 if (!dtg)
159 dcss->dtg = dtg;
160 dtg->dev = dcss->dev;
161 dtg->ctxld = dcss->ctxld;
163 dtg->base_reg = ioremap(dtg_base, SZ_4K);
164 if (!dtg->base_reg) {
165 dev_err(dcss->dev, "dtg: unable to remap dtg base\n");
170 dtg->base_ofs = dtg_base;
171 dtg->ctx_id = CTX_DB;
173 dtg->alpha = 255;
175 dtg->control_status |= OVL_DATA_MODE | BLENDER_VIDEO_ALPHA_SEL |
176 ((dtg->alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK);
178 ret = dcss_dtg_irq_config(dtg, to_platform_device(dcss->dev));
185 iounmap(dtg->base_reg);
188 kfree(dtg);
193 void dcss_dtg_exit(struct dcss_dtg *dtg)
195 free_irq(dtg->ctxld_kick_irq, dtg);
197 if (dtg->base_reg)
198 iounmap(dtg->base_reg);
200 kfree(dtg);
203 void dcss_dtg_sync_set(struct dcss_dtg *dtg, struct videomode *vm)
205 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(dtg->dev);
229 dev_info(dtg->dev,
234 dcss_dtg_write(dtg, ((dtg_lrc_y << TC_Y_POS) | dtg_lrc_x),
236 dcss_dtg_write(dtg, ((dis_ulc_y << TC_Y_POS) | dis_ulc_x),
238 dcss_dtg_write(dtg, ((dis_lrc_y << TC_Y_POS) | dis_lrc_x),
241 dtg->dis_ulc_x = dis_ulc_x;
242 dtg->dis_ulc_y = dis_ulc_y;
249 dcss_dtg_write(dtg, sb_ctxld_trig | db_ctxld_trig, DCSS_DTG_TC_CTXLD);
252 dcss_dtg_write(dtg, 0, DCSS_DTG_LINE1_INT);
255 dcss_dtg_write(dtg, ((90 * dis_lrc_y) / 100) << 16, DCSS_DTG_LINE0_INT);
258 void dcss_dtg_plane_pos_set(struct dcss_dtg *dtg, int ch_num,
264 p_ulc_x = dtg->dis_ulc_x + px;
265 p_ulc_y = dtg->dis_ulc_y + py;
270 dcss_dtg_write(dtg, 0, DCSS_DTG_TC_CH1_TOP + 0x8 * ch_num);
271 dcss_dtg_write(dtg, 0, DCSS_DTG_TC_CH1_BOT + 0x8 * ch_num);
273 dcss_dtg_write(dtg, ((p_ulc_y << TC_Y_POS) | p_ulc_x),
275 dcss_dtg_write(dtg, ((p_lrc_y << TC_Y_POS) | p_lrc_x),
280 bool dcss_dtg_global_alpha_changed(struct dcss_dtg *dtg, int ch_num, int alpha)
285 return alpha != dtg->alpha;
288 void dcss_dtg_plane_alpha_set(struct dcss_dtg *dtg, int ch_num,
300 dtg->alpha_cfg = (alpha << DEFAULT_FG_ALPHA_POS) & DEFAULT_FG_ALPHA_MASK;
302 dtg->alpha_cfg = CH1_ALPHA_SEL;
304 dtg->alpha = alpha;
307 void dcss_dtg_css_set(struct dcss_dtg *dtg)
309 dtg->control_status |=
313 void dcss_dtg_enable(struct dcss_dtg *dtg)
315 dtg->control_status |= DTG_START;
317 dtg->control_status &= ~(CH1_ALPHA_SEL | DEFAULT_FG_ALPHA_MASK);
318 dtg->control_status |= dtg->alpha_cfg;
320 dcss_dtg_write(dtg, dtg->control_status, DCSS_DTG_TC_CONTROL_STATUS);
322 dtg->in_use = true;
325 void dcss_dtg_shutoff(struct dcss_dtg *dtg)
327 dtg->control_status &= ~DTG_START;
329 dcss_writel(dtg->control_status,
330 dtg->base_reg + DCSS_DTG_TC_CONTROL_STATUS);
332 dtg->in_use = false;
335 bool dcss_dtg_is_enabled(struct dcss_dtg *dtg)
337 return dtg->in_use;
340 void dcss_dtg_ch_enable(struct dcss_dtg *dtg, int ch_num, bool en)
345 control_status = dtg->control_status & ~ch_en_map[ch_num];
349 control_status |= dtg->alpha_cfg;
351 if (dtg->control_status != control_status)
352 dcss_dtg_write(dtg, control_status, DCSS_DTG_TC_CONTROL_STATUS);
354 dtg->control_status = control_status;
357 void dcss_dtg_vblank_irq_enable(struct dcss_dtg *dtg, bool en)
363 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
365 dtg->base_reg + DCSS_DTG_INT_CONTROL);
368 dcss_update(mask, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);
371 void dcss_dtg_ctxld_kick_irq_enable(struct dcss_dtg *dtg, bool en)
377 status = dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS);
379 if (!dtg->ctxld_kick_irq_en) {
381 dtg->base_reg + DCSS_DTG_INT_CONTROL);
382 enable_irq(dtg->ctxld_kick_irq);
383 dtg->ctxld_kick_irq_en = true;
385 dtg->base_reg + DCSS_DTG_INT_MASK);
391 if (!dtg->ctxld_kick_irq_en)
394 disable_irq_nosync(dtg->ctxld_kick_irq);
395 dtg->ctxld_kick_irq_en = false;
397 dcss_update(mask, LINE0_IRQ, dtg->base_reg + DCSS_DTG_INT_MASK);
400 void dcss_dtg_vblank_irq_clear(struct dcss_dtg *dtg)
402 dcss_update(LINE1_IRQ, LINE1_IRQ, dtg->base_reg + DCSS_DTG_INT_CONTROL);
405 bool dcss_dtg_vblank_irq_valid(struct dcss_dtg *dtg)
407 return !!(dcss_readl(dtg->base_reg + DCSS_DTG_INT_STATUS) & LINE1_IRQ);