Lines Matching defs:ctxld
90 struct dcss_ctxld *ctxld = data;
91 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(ctxld->dev);
94 irq_status = dcss_readl(ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
97 !(irq_status & CTXLD_ENABLE) && ctxld->in_use) {
98 ctxld->in_use = false;
107 dev_err(ctxld->dev, "ctxld: error encountered: %08x\n",
109 dev_err(ctxld->dev, "ctxld: db=%d, sb_hp=%d, sb_lp=%d\n",
110 ctxld->ctx_size[ctxld->current_ctx ^ 1][CTX_DB],
111 ctxld->ctx_size[ctxld->current_ctx ^ 1][CTX_SB_HP],
112 ctxld->ctx_size[ctxld->current_ctx ^ 1][CTX_SB_LP]);
116 ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
121 static int dcss_ctxld_irq_config(struct dcss_ctxld *ctxld,
126 ctxld->irq = platform_get_irq_byname(pdev, "ctxld");
127 if (ctxld->irq < 0)
128 return ctxld->irq;
130 ret = request_irq(ctxld->irq, dcss_ctxld_irq_handler,
131 0, "dcss_ctxld", ctxld);
133 dev_err(ctxld->dev, "ctxld: irq request failed.\n");
137 ctxld->irq_en = true;
142 static void dcss_ctxld_hw_cfg(struct dcss_ctxld *ctxld)
146 ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
149 static void dcss_ctxld_free_ctx(struct dcss_ctxld *ctxld)
155 if (ctxld->db[i]) {
156 dma_free_coherent(ctxld->dev,
158 ctxld->db[i], ctxld->db_paddr[i]);
159 ctxld->db[i] = NULL;
160 ctxld->db_paddr[i] = 0;
163 if (ctxld->sb_hp[i]) {
164 dma_free_coherent(ctxld->dev,
166 ctxld->sb_hp[i], ctxld->sb_paddr[i]);
167 ctxld->sb_hp[i] = NULL;
168 ctxld->sb_paddr[i] = 0;
173 static int dcss_ctxld_alloc_ctx(struct dcss_ctxld *ctxld)
179 ctx = dma_alloc_coherent(ctxld->dev,
181 &ctxld->db_paddr[i], GFP_KERNEL);
185 ctxld->db[i] = ctx;
187 ctx = dma_alloc_coherent(ctxld->dev,
189 &ctxld->sb_paddr[i], GFP_KERNEL);
193 ctxld->sb_hp[i] = ctx;
194 ctxld->sb_lp[i] = ctx + CTXLD_SB_HP_CTX_ENTRIES;
202 struct dcss_ctxld *ctxld;
205 ctxld = kzalloc(sizeof(*ctxld), GFP_KERNEL);
206 if (!ctxld)
209 dcss->ctxld = ctxld;
210 ctxld->dev = dcss->dev;
212 spin_lock_init(&ctxld->lock);
214 ret = dcss_ctxld_alloc_ctx(ctxld);
216 dev_err(dcss->dev, "ctxld: cannot allocate context memory.\n");
220 ctxld->ctxld_reg = ioremap(ctxld_base, SZ_4K);
221 if (!ctxld->ctxld_reg) {
222 dev_err(dcss->dev, "ctxld: unable to remap ctxld base\n");
227 ret = dcss_ctxld_irq_config(ctxld, to_platform_device(dcss->dev));
231 dcss_ctxld_hw_cfg(ctxld);
236 iounmap(ctxld->ctxld_reg);
239 dcss_ctxld_free_ctx(ctxld);
240 kfree(ctxld);
245 void dcss_ctxld_exit(struct dcss_ctxld *ctxld)
247 free_irq(ctxld->irq, ctxld);
249 if (ctxld->ctxld_reg)
250 iounmap(ctxld->ctxld_reg);
252 dcss_ctxld_free_ctx(ctxld);
253 kfree(ctxld);
256 static int dcss_ctxld_enable_locked(struct dcss_ctxld *ctxld)
258 int curr_ctx = ctxld->current_ctx;
261 struct dcss_dev *dcss = dcss_drv_dev_to_dcss(ctxld->dev);
270 sb_hp_cnt = ctxld->ctx_size[curr_ctx][CTX_SB_HP];
271 sb_lp_cnt = ctxld->ctx_size[curr_ctx][CTX_SB_LP];
272 db_cnt = ctxld->ctx_size[curr_ctx][CTX_DB];
276 ctxld->sb_lp[curr_ctx] != ctxld->sb_hp[curr_ctx] + sb_hp_cnt) {
279 sb_lp_adjusted = ctxld->sb_hp[curr_ctx] + sb_hp_cnt;
281 memcpy(sb_lp_adjusted, ctxld->sb_lp[curr_ctx],
285 db_base = db_cnt ? ctxld->db_paddr[curr_ctx] : 0;
287 dcss_writel(db_base, ctxld->ctxld_reg + DCSS_CTXLD_DB_BASE_ADDR);
288 dcss_writel(db_cnt, ctxld->ctxld_reg + DCSS_CTXLD_DB_COUNT);
296 sb_base = sb_count ? ctxld->sb_paddr[curr_ctx] : 0;
298 dcss_writel(sb_base, ctxld->ctxld_reg + DCSS_CTXLD_SB_BASE_ADDR);
299 dcss_writel(sb_count, ctxld->ctxld_reg + DCSS_CTXLD_SB_COUNT);
302 dcss_set(CTXLD_ENABLE, ctxld->ctxld_reg + DCSS_CTXLD_CONTROL_STATUS);
304 ctxld->in_use = true;
310 ctxld->current_ctx ^= 1;
312 ctxld->ctx_size[ctxld->current_ctx][CTX_DB] = 0;
313 ctxld->ctx_size[ctxld->current_ctx][CTX_SB_HP] = 0;
314 ctxld->ctx_size[ctxld->current_ctx][CTX_SB_LP] = 0;
319 int dcss_ctxld_enable(struct dcss_ctxld *ctxld)
321 spin_lock_irq(&ctxld->lock);
322 ctxld->armed = true;
323 spin_unlock_irq(&ctxld->lock);
328 void dcss_ctxld_kick(struct dcss_ctxld *ctxld)
332 spin_lock_irqsave(&ctxld->lock, flags);
333 if (ctxld->armed && !ctxld->in_use) {
334 ctxld->armed = false;
335 dcss_ctxld_enable_locked(ctxld);
337 spin_unlock_irqrestore(&ctxld->lock, flags);
340 void dcss_ctxld_write_irqsafe(struct dcss_ctxld *ctxld, u32 ctx_id, u32 val,
343 int curr_ctx = ctxld->current_ctx;
345 [CTX_DB] = ctxld->db[curr_ctx],
346 [CTX_SB_HP] = ctxld->sb_hp[curr_ctx],
347 [CTX_SB_LP] = ctxld->sb_lp[curr_ctx]
349 int item_idx = ctxld->ctx_size[curr_ctx][ctx_id];
358 ctxld->ctx_size[curr_ctx][ctx_id] += 1;
361 void dcss_ctxld_write(struct dcss_ctxld *ctxld, u32 ctx_id,
364 spin_lock_irq(&ctxld->lock);
365 dcss_ctxld_write_irqsafe(ctxld, ctx_id, val, reg_ofs);
366 spin_unlock_irq(&ctxld->lock);
369 bool dcss_ctxld_is_flushed(struct dcss_ctxld *ctxld)
371 return ctxld->ctx_size[ctxld->current_ctx][CTX_DB] == 0 &&
372 ctxld->ctx_size[ctxld->current_ctx][CTX_SB_HP] == 0 &&
373 ctxld->ctx_size[ctxld->current_ctx][CTX_SB_LP] == 0;
376 int dcss_ctxld_resume(struct dcss_ctxld *ctxld)
378 dcss_ctxld_hw_cfg(ctxld);
380 if (!ctxld->irq_en) {
381 enable_irq(ctxld->irq);
382 ctxld->irq_en = true;
388 int dcss_ctxld_suspend(struct dcss_ctxld *ctxld)
393 if (!dcss_ctxld_is_flushed(ctxld)) {
394 dcss_ctxld_kick(ctxld);
396 while (!time_after(jiffies, timeout) && ctxld->in_use)
403 spin_lock_irq(&ctxld->lock);
405 if (ctxld->irq_en) {
406 disable_irq_nosync(ctxld->irq);
407 ctxld->irq_en = false;
411 ctxld->current_ctx = 0;
412 ctxld->ctx_size[0][CTX_DB] = 0;
413 ctxld->ctx_size[0][CTX_SB_HP] = 0;
414 ctxld->ctx_size[0][CTX_SB_LP] = 0;
416 spin_unlock_irq(&ctxld->lock);
421 void dcss_ctxld_assert_locked(struct dcss_ctxld *ctxld)
423 lockdep_assert_held(&ctxld->lock);