Lines Matching refs:i915
48 static void __vlv_punit_get(struct drm_i915_private *i915)
62 if (IS_VALLEYVIEW(i915)) {
63 cpu_latency_qos_update_request(&i915->sb_qos, 0);
68 static void __vlv_punit_put(struct drm_i915_private *i915)
70 if (IS_VALLEYVIEW(i915))
71 cpu_latency_qos_update_request(&i915->sb_qos,
77 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
80 __vlv_punit_get(i915);
82 mutex_lock(&i915->sb_lock);
85 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
87 mutex_unlock(&i915->sb_lock);
90 __vlv_punit_put(i915);
93 static int vlv_sideband_rw(struct drm_i915_private *i915,
97 struct intel_uncore *uncore = &i915->uncore;
101 lockdep_assert_held(&i915->sb_lock);
109 drm_dbg(&i915->drm, "IOSF sideband idle wait (%s) timed out\n",
133 drm_dbg(&i915->drm, "IOSF sideband finish wait (%s) timed out\n",
143 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
147 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
153 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
155 return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
159 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
163 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
169 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
171 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
175 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
179 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
185 u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
189 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
195 void vlv_iosf_sb_write(struct drm_i915_private *i915,
198 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
202 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
206 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
212 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
214 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
218 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
222 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
228 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
230 vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
234 static u32 vlv_dpio_phy_iosf_port(struct drm_i915_private *i915, enum dpio_phy phy)
240 if (IS_CHERRYVIEW(i915))
246 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
248 u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
251 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
257 drm_WARN(&i915->drm, val == 0xffffffff,
264 void vlv_dpio_write(struct drm_i915_private *i915,
267 u32 port = vlv_dpio_phy_iosf_port(i915, DPIO_PHY(pipe));
269 vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
272 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
276 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
281 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
283 vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
288 static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
292 struct intel_uncore *uncore = &i915->uncore;
295 lockdep_assert_held(&i915->sb_lock);
300 drm_err(&i915->drm,
319 drm_err(&i915->drm,
325 drm_err(&i915->drm, "error during SBI read of reg %x\n", reg);
335 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
340 intel_sbi_rw(i915, reg, destination, &result, true);
345 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
348 intel_sbi_rw(i915, reg, destination, &value, false);
396 static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
402 struct intel_uncore *uncore = &i915->uncore;
404 lockdep_assert_held(&i915->sb_lock);
433 if (INTEL_GEN(i915) > 6)
439 int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox,
444 mutex_lock(&i915->sb_lock);
445 err = __sandybridge_pcode_rw(i915, mbox, val, val1,
448 mutex_unlock(&i915->sb_lock);
451 drm_dbg(&i915->drm,
459 int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
466 mutex_lock(&i915->sb_lock);
467 err = __sandybridge_pcode_rw(i915, mbox, &val, NULL,
470 mutex_unlock(&i915->sb_lock);
473 drm_dbg(&i915->drm,
481 static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
485 *status = __sandybridge_pcode_rw(i915, mbox, &request, NULL,
494 * @i915: device private
511 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
517 mutex_lock(&i915->sb_lock);
520 skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
546 drm_dbg_kms(&i915->drm,
548 drm_WARN_ON_ONCE(&i915->drm, timeout_base_ms > 3);
554 mutex_unlock(&i915->sb_lock);
559 void intel_pcode_init(struct drm_i915_private *i915)
563 if (!IS_DGFX(i915))
566 ret = skl_pcode_request(i915, DG1_PCODE_STATUS,
571 drm_err(&i915->drm, "Pcode did not report uncore initialization completion!\n");