Lines Matching refs:wm
455 mutex_lock(&dev_priv->wm.wm_mutex);
458 dev_priv->wm.vlv.cxsr = enable;
460 dev_priv->wm.g4x.cxsr = enable;
461 mutex_unlock(&dev_priv->wm.wm_mutex);
489 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
752 * @wm: chip FIFO params
769 const struct intel_watermark_params *wm,
783 entries = DIV_ROUND_UP(entries, wm->cacheline_size) +
784 wm->guard_size;
791 if (wm_size > wm->max_wm)
792 wm_size = wm->max_wm;
794 wm_size = wm->default_wm;
821 return dev_priv->wm.max_level + 1;
887 unsigned int wm;
910 wm = intel_calculate_wm(clock, &pnv_display_wm,
915 reg |= FW_WM(wm, SR);
920 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
925 reg |= FW_WM(wm, CURSOR_SR);
929 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
934 reg |= FW_WM(wm, HPLL_SR);
938 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
943 reg |= FW_WM(wm, HPLL_CURSOR);
971 const struct g4x_wm_values *wm)
976 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
979 FW_WM(wm->sr.plane, SR) |
980 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
981 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
982 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
984 (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) |
985 FW_WM(wm->sr.fbc, FBC_SR) |
986 FW_WM(wm->hpll.fbc, FBC_HPLL_SR) |
987 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
988 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
989 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
991 (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) |
992 FW_WM(wm->sr.cursor, CURSOR_SR) |
993 FW_WM(wm->hpll.cursor, HPLL_CURSOR) |
994 FW_WM(wm->hpll.plane, HPLL_SR));
1003 const struct vlv_wm_values *wm)
1008 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1011 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1012 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1013 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1014 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1029 FW_WM(wm->sr.plane, SR) |
1030 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1031 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1032 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1034 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1035 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1036 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1038 FW_WM(wm->sr.cursor, CURSOR_SR));
1042 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1043 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1045 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1046 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1048 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1049 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1051 FW_WM(wm->sr.plane >> 9, SR_HI) |
1052 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1053 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1054 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1055 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1056 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1057 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1058 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1059 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1060 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1063 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1064 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1066 FW_WM(wm->sr.plane >> 9, SR_HI) |
1067 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1068 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1069 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1070 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1071 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1072 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1083 dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5;
1084 dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12;
1085 dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35;
1087 dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL;
1140 unsigned int latency = dev_priv->wm.pri_latency[level] * 10;
1141 unsigned int clock, htotal, cpp, width, wm;
1172 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1175 wm = intel_wm_method1(clock, cpp, latency);
1182 wm = min(small, large);
1185 wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level),
1188 wm = DIV_ROUND_UP(wm, 64) + 2;
1190 return min_t(unsigned int, wm, USHRT_MAX);
1200 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1219 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1250 struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1251 int wm, max_wm;
1253 wm = g4x_compute_wm(crtc_state, plane_state, level);
1256 if (wm > max_wm)
1259 dirty |= raw->plane[plane_id] != wm;
1260 raw->plane[plane_id] = wm;
1266 wm = ilk_compute_fbc_wm(crtc_state, plane_state,
1271 * FBC wm is not mandatory as we
1274 if (wm > max_wm)
1275 wm = USHRT_MAX;
1277 dirty |= raw->fbc != wm;
1278 raw->fbc = wm;
1292 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id],
1293 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id],
1294 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]);
1299 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc,
1300 crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc);
1309 const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level];
1319 if (level > dev_priv->wm.max_level)
1335 wm_state->wm.plane[plane_id] = USHRT_MAX;
1375 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
1404 raw = &crtc_state->wm.g4x.raw[level];
1406 wm_state->wm.plane[plane_id] = raw->plane[plane_id];
1412 raw = &crtc_state->wm.g4x.raw[level];
1423 raw = &crtc_state->wm.g4x.raw[level];
1455 struct g4x_wm_state *intermediate = &new_crtc_state->wm.g4x.intermediate;
1456 const struct g4x_wm_state *optimal = &new_crtc_state->wm.g4x.optimal;
1461 const struct g4x_wm_state *active = &old_crtc_state->wm.g4x.optimal;
1479 intermediate->wm.plane[plane_id] =
1480 max(optimal->wm.plane[plane_id],
1481 active->wm.plane[plane_id]);
1483 drm_WARN_ON(&dev_priv->drm, intermediate->wm.plane[plane_id] >
1527 new_crtc_state->wm.need_postvbl_update = true;
1533 struct g4x_wm_values *wm)
1538 wm->cxsr = true;
1539 wm->hpll_en = true;
1540 wm->fbc_en = true;
1543 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1549 wm->cxsr = false;
1551 wm->hpll_en = false;
1553 wm->fbc_en = false;
1559 wm->cxsr = false;
1560 wm->hpll_en = false;
1561 wm->fbc_en = false;
1565 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1568 wm->pipe[pipe] = wm_state->wm;
1569 if (crtc->active && wm->cxsr)
1570 wm->sr = wm_state->sr;
1571 if (crtc->active && wm->hpll_en)
1572 wm->hpll = wm_state->hpll;
1578 struct g4x_wm_values *old_wm = &dev_priv->wm.g4x;
1604 mutex_lock(&dev_priv->wm.wm_mutex);
1605 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1607 mutex_unlock(&dev_priv->wm.wm_mutex);
1617 if (!crtc_state->wm.need_postvbl_update)
1620 mutex_lock(&dev_priv->wm.wm_mutex);
1621 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1623 mutex_unlock(&dev_priv->wm.wm_mutex);
1645 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
1647 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
1650 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
1651 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
1653 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
1665 unsigned int clock, htotal, cpp, width, wm;
1667 if (dev_priv->wm.pri_latency[level] == 0)
1685 wm = 63;
1687 wm = vlv_wm_method2(clock, htotal, width, cpp,
1688 dev_priv->wm.pri_latency[level] * 10);
1691 return min_t(unsigned int, wm, USHRT_MAX);
1705 &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2];
1706 struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state;
1793 wm_state->wm[level].plane[plane_id] = USHRT_MAX;
1800 static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size)
1802 if (wm > fifo_size)
1805 return fifo_size - wm;
1820 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1845 struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1846 int wm = vlv_compute_wm_level(crtc_state, plane_state, level);
1849 if (wm > max_wm)
1852 dirty |= raw->plane[plane_id] != wm;
1853 raw->plane[plane_id] = wm;
1864 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id],
1865 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id],
1866 crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]);
1875 &crtc_state->wm.vlv.raw[level];
1877 &crtc_state->wm.vlv.fifo_state;
1896 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
1898 &crtc_state->wm.vlv.fifo_state;
1937 &old_crtc_state->wm.vlv.fifo_state;
1959 const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level];
1966 wm_state->wm[level].plane[plane_id] =
2005 &crtc_state->wm.vlv.fifo_state;
2098 struct vlv_wm_state *intermediate = &new_crtc_state->wm.vlv.intermediate;
2099 const struct vlv_wm_state *optimal = &new_crtc_state->wm.vlv.optimal;
2104 const struct vlv_wm_state *active = &old_crtc_state->wm.vlv.optimal;
2122 intermediate->wm[level].plane[plane_id] =
2123 min(optimal->wm[level].plane[plane_id],
2124 active->wm[level].plane[plane_id]);
2141 new_crtc_state->wm.need_postvbl_update = true;
2147 struct vlv_wm_values *wm)
2152 wm->level = dev_priv->wm.max_level;
2153 wm->cxsr = true;
2156 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2162 wm->cxsr = false;
2165 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
2169 wm->cxsr = false;
2172 wm->level = VLV_WM_LEVEL_PM2;
2175 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2178 wm->pipe[pipe] = wm_state->wm[wm->level];
2179 if (crtc->active && wm->cxsr)
2180 wm->sr = wm_state->sr[wm->level];
2182 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2183 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2184 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2185 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
2191 struct vlv_wm_values *old_wm = &dev_priv->wm.vlv;
2229 mutex_lock(&dev_priv->wm.wm_mutex);
2230 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2232 mutex_unlock(&dev_priv->wm.wm_mutex);
2242 if (!crtc_state->wm.need_postvbl_update)
2245 mutex_lock(&dev_priv->wm.wm_mutex);
2246 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2248 mutex_unlock(&dev_priv->wm.wm_mutex);
2282 "self-refresh entries: %d, wm: %d\n",
2822 u16 pri_latency = dev_priv->wm.pri_latency[level];
2823 u16 spr_latency = dev_priv->wm.spr_latency[level];
2824 u16 cur_latency = dev_priv->wm.cur_latency[level];
2849 u16 wm[])
2870 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2871 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2873 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2875 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2889 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2890 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2892 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2894 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2903 if (wm[level] == 0) {
2905 wm[i] = 0;
2917 if (wm[0] == 0) {
2918 wm[0] += 2;
2920 if (wm[level] == 0)
2922 wm[level] += 2;
2933 wm[0] += 1;
2938 wm[0] = (sskpd >> 56) & 0xFF;
2939 if (wm[0] == 0)
2940 wm[0] = sskpd & 0xF;
2941 wm[1] = (sskpd >> 4) & 0xFF;
2942 wm[2] = (sskpd >> 12) & 0xFF;
2943 wm[3] = (sskpd >> 20) & 0x1FF;
2944 wm[4] = (sskpd >> 32) & 0x1FF;
2948 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2949 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2950 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2951 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2956 wm[0] = 7;
2957 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2958 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2965 u16 wm[5])
2969 wm[0] = 13;
2973 u16 wm[5])
2977 wm[0] = 13;
2995 const u16 wm[])
3000 unsigned int latency = wm[level];
3020 wm[level], latency / 10, latency % 10);
3025 u16 wm[5], u16 min)
3029 if (wm[0] >= min)
3032 wm[0] = max(wm[0], min);
3034 wm[level] = max_t(u16, wm[level], DIV_ROUND_UP(min, 5));
3047 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12);
3048 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12);
3049 changed |= ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
3056 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3057 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3058 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3074 if (dev_priv->wm.pri_latency[3] == 0 &&
3075 dev_priv->wm.spr_latency[3] == 0 &&
3076 dev_priv->wm.cur_latency[3] == 0)
3079 dev_priv->wm.pri_latency[3] = 0;
3080 dev_priv->wm.spr_latency[3] = 0;
3081 dev_priv->wm.cur_latency[3] = 0;
3085 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3086 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3087 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3092 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
3094 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
3095 sizeof(dev_priv->wm.pri_latency));
3096 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
3097 sizeof(dev_priv->wm.pri_latency));
3099 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
3100 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
3102 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
3103 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
3104 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
3114 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
3115 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
3133 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
3155 pipe_wm = &crtc_state->wm.ilk.optimal;
3184 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
3186 pristate, sprstate, curstate, &pipe_wm->wm[0]);
3194 struct intel_wm_level *wm = &pipe_wm->wm[level];
3197 pristate, sprstate, curstate, wm);
3204 if (!ilk_validate_wm_level(level, &max, wm)) {
3205 memset(wm, 0, sizeof(*wm));
3222 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
3227 const struct intel_pipe_wm *b = &oldstate->wm.ilk.optimal;
3235 *a = newstate->wm.ilk.optimal;
3245 struct intel_wm_level *a_wm = &a->wm[level];
3246 const struct intel_wm_level *b_wm = &b->wm[level];
3268 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0)
3269 newstate->wm.need_postvbl_update = true;
3286 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
3287 const struct intel_wm_level *wm = &active->wm[level];
3297 if (!wm->enable)
3300 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
3301 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
3302 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
3303 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
3328 struct intel_wm_level *wm = &merged->wm[level];
3330 ilk_merge_wm_level(dev_priv, level, wm);
3333 wm->enable = false;
3334 else if (!ilk_validate_wm_level(level, max, wm))
3342 if (wm->fbc_val > max->fbc) {
3343 if (wm->enable)
3345 wm->fbc_val = 0;
3358 struct intel_wm_level *wm = &merged->wm[level];
3360 wm->enable = false;
3368 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
3378 return dev_priv->wm.pri_latency[level];
3398 r = &merged->wm[level];
3433 const struct intel_pipe_wm *pipe_wm = &intel_crtc->wm.active.ilk;
3434 const struct intel_wm_level *r = &pipe_wm->wm[0];
3457 if (r1->wm[level].enable)
3459 if (r2->wm[level].enable)
3531 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3565 struct ilk_wm_values *previous = &dev_priv->wm.hw;
3627 dev_priv->wm.hw = *results;
3890 const struct skl_plane_wm *wm =
3891 &crtc_state->wm.skl.optimal.planes[plane->id];
3894 if (!wm->wm[0].plane_en)
3897 /* Find the highest enabled wm level for this plane */
3899 !wm->wm[level].plane_en; --level)
3902 latency = dev_priv->wm.skl_latency[level];
3910 * If any of the planes on this pipe don't enable wm levels that
3931 &crtc_state->wm.skl.plane_ddb_y[plane_id];
3932 const struct skl_plane_wm *wm =
3933 &crtc_state->wm.skl.optimal.planes[plane_id];
3935 if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
4012 struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
4139 !dev_priv->wm.distrust_bios_wm) {
4146 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
4263 struct skl_wm_level wm = {};
4275 unsigned int latency = dev_priv->wm.skl_latency[level];
4277 skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
4278 if (wm.min_ddb_alloc == U16_MAX)
4281 min_ddb_alloc = wm.min_ddb_alloc;
4784 const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
4785 const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
4788 return &wm->sagv_wm0;
4790 return &wm->wm[level];
4798 struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
4812 memset(crtc_state->wm.skl.plane_ddb_y, 0, sizeof(crtc_state->wm.skl.plane_ddb_y));
4813 memset(crtc_state->wm.skl.plane_ddb_uv, 0, sizeof(crtc_state->wm.skl.plane_ddb_uv));
4867 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
4869 crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
4881 const struct skl_plane_wm *wm =
4882 &crtc_state->wm.skl.optimal.planes[plane_id];
4885 if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
4887 wm->wm[level].min_ddb_alloc != U16_MAX);
4894 blocks += wm->wm[level].min_ddb_alloc;
4895 blocks += wm->uv_wm[level].min_ddb_alloc;
4918 const struct skl_plane_wm *wm =
4919 &crtc_state->wm.skl.optimal.planes[plane_id];
4937 total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
4948 uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
4958 &crtc_state->wm.skl.plane_ddb_y[plane_id];
4960 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
4991 struct skl_plane_wm *wm =
4992 &crtc_state->wm.skl.optimal.planes[plane_id];
5006 if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
5007 wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
5008 memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
5015 level == 1 && wm->wm[0].plane_en) {
5016 wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
5017 wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
5018 wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
5028 struct skl_plane_wm *wm =
5029 &crtc_state->wm.skl.optimal.planes[plane_id];
5031 if (wm->trans_wm.plane_res_b >= total[plane_id])
5032 memset(&wm->trans_wm, 0, sizeof(wm->trans_wm));
5393 unsigned int latency = dev_priv->wm.skl_latency[level];
5408 struct skl_wm_level *levels = plane_wm->wm;
5409 unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
5418 struct skl_plane_wm *wm)
5459 wm0_sel_res_b = wm->wm[0].plane_res_b - 1;
5475 wm->trans_wm.plane_res_b = res_blocks + 1;
5476 wm->trans_wm.plane_en = true;
5485 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5494 skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
5497 tgl_compute_sagv_wm(crtc_state, &wm_params, wm);
5499 skl_compute_transition_wm(crtc_state, &wm_params, wm);
5508 struct skl_plane_wm *wm = &crtc_state->wm.skl.optimal.planes[plane_id];
5512 wm->is_planar = true;
5520 skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
5593 struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
5652 const struct skl_plane_wm *wm =
5653 &crtc_state->wm.skl.optimal.planes[plane_id];
5655 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5657 &crtc_state->wm.skl.plane_ddb_uv[plane_id];
5668 &wm->trans_wm);
5676 if (wm->is_planar)
5692 const struct skl_plane_wm *wm =
5693 &crtc_state->wm.skl.optimal.planes[plane_id];
5695 &crtc_state->wm.skl.plane_ddb_y[plane_id];
5705 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5731 if (!skl_wm_level_equals(&wm1->wm[level], &wm2->wm[level]))
5772 if (skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_y[plane_id],
5773 &new_crtc_state->wm.skl.plane_ddb_y[plane_id]) &&
5774 skl_ddb_entry_equal(&old_crtc_state->wm.skl.plane_ddb_uv[plane_id],
5775 &new_crtc_state->wm.skl.plane_ddb_uv[plane_id]))
5847 old_pipe_wm = &old_crtc_state->wm.skl.optimal;
5848 new_pipe_wm = &new_crtc_state->wm.skl.optimal;
5854 old = &old_crtc_state->wm.skl.plane_ddb_y[plane_id];
5855 new = &new_crtc_state->wm.skl.plane_ddb_y[plane_id];
5881 enast(old_wm->wm[0].plane_en), enast(old_wm->wm[1].plane_en),
5882 enast(old_wm->wm[2].plane_en), enast(old_wm->wm[3].plane_en),
5883 enast(old_wm->wm[4].plane_en), enast(old_wm->wm[5].plane_en),
5884 enast(old_wm->wm[6].plane_en), enast(old_wm->wm[7].plane_en),
5887 enast(new_wm->wm[0].plane_en), enast(new_wm->wm[1].plane_en),
5888 enast(new_wm->wm[2].plane_en), enast(new_wm->wm[3].plane_en),
5889 enast(new_wm->wm[4].plane_en), enast(new_wm->wm[5].plane_en),
5890 enast(new_wm->wm[6].plane_en), enast(new_wm->wm[7].plane_en),
5898 enast(old_wm->wm[0].ignore_lines), old_wm->wm[0].plane_res_l,
5899 enast(old_wm->wm[1].ignore_lines), old_wm->wm[1].plane_res_l,
5900 enast(old_wm->wm[2].ignore_lines), old_wm->wm[2].plane_res_l,
5901 enast(old_wm->wm[3].ignore_lines), old_wm->wm[3].plane_res_l,
5902 enast(old_wm->wm[4].ignore_lines), old_wm->wm[4].plane_res_l,
5903 enast(old_wm->wm[5].ignore_lines), old_wm->wm[5].plane_res_l,
5904 enast(old_wm->wm[6].ignore_lines), old_wm->wm[6].plane_res_l,
5905 enast(old_wm->wm[7].ignore_lines), old_wm->wm[7].plane_res_l,
5909 enast(new_wm->wm[0].ignore_lines), new_wm->wm[0].plane_res_l,
5910 enast(new_wm->wm[1].ignore_lines), new_wm->wm[1].plane_res_l,
5911 enast(new_wm->wm[2].ignore_lines), new_wm->wm[2].plane_res_l,
5912 enast(new_wm->wm[3].ignore_lines), new_wm->wm[3].plane_res_l,
5913 enast(new_wm->wm[4].ignore_lines), new_wm->wm[4].plane_res_l,
5914 enast(new_wm->wm[5].ignore_lines), new_wm->wm[5].plane_res_l,
5915 enast(new_wm->wm[6].ignore_lines), new_wm->wm[6].plane_res_l,
5916 enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
5924 old_wm->wm[0].plane_res_b, old_wm->wm[1].plane_res_b,
5925 old_wm->wm[2].plane_res_b, old_wm->wm[3].plane_res_b,
5926 old_wm->wm[4].plane_res_b, old_wm->wm[5].plane_res_b,
5927 old_wm->wm[6].plane_res_b, old_wm->wm[7].plane_res_b,
5930 new_wm->wm[0].plane_res_b, new_wm->wm[1].plane_res_b,
5931 new_wm->wm[2].plane_res_b, new_wm->wm[3].plane_res_b,
5932 new_wm->wm[4].plane_res_b, new_wm->wm[5].plane_res_b,
5933 new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
5941 old_wm->wm[0].min_ddb_alloc, old_wm->wm[1].min_ddb_alloc,
5942 old_wm->wm[2].min_ddb_alloc, old_wm->wm[3].min_ddb_alloc,
5943 old_wm->wm[4].min_ddb_alloc, old_wm->wm[5].min_ddb_alloc,
5944 old_wm->wm[6].min_ddb_alloc, old_wm->wm[7].min_ddb_alloc,
5947 new_wm->wm[0].min_ddb_alloc, new_wm->wm[1].min_ddb_alloc,
5948 new_wm->wm[2].min_ddb_alloc, new_wm->wm[3].min_ddb_alloc,
5949 new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
5950 new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
5985 if (dev_priv->wm.distrust_bios_wm) {
6071 * Force a full wm update for every plane on modeset.
6072 * Required because the reset value of the wm registers
6080 &old_crtc_state->wm.skl.optimal.planes[plane_id],
6081 &new_crtc_state->wm.skl.optimal.planes[plane_id]))
6150 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
6152 if (!wm->pipe_enabled)
6155 config->sprites_enabled |= wm->sprites_enabled;
6156 config->sprites_scaled |= wm->sprites_scaled;
6200 mutex_lock(&dev_priv->wm.wm_mutex);
6201 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
6203 mutex_unlock(&dev_priv->wm.wm_mutex);
6213 if (!crtc_state->wm.need_postvbl_update)
6216 mutex_lock(&dev_priv->wm.wm_mutex);
6217 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
6219 mutex_unlock(&dev_priv->wm.wm_mutex);
6243 struct skl_plane_wm *wm = &out->planes[plane_id];
6251 skl_wm_level_from_reg_val(val, &wm->wm[level]);
6255 wm->sagv_wm0 = wm->wm[0];
6262 skl_wm_level_from_reg_val(val, &wm->trans_wm);
6277 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
6282 dev_priv->wm.distrust_bios_wm = true;
6290 struct ilk_wm_values *hw = &dev_priv->wm.hw;
6292 struct intel_pipe_wm *active = &crtc_state->wm.ilk.optimal;
6315 active->wm[0].enable = true;
6316 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
6317 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
6318 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
6328 active->wm[level].enable = true;
6331 crtc->wm.active.ilk = *active;
6340 struct g4x_wm_values *wm)
6345 wm->sr.plane = _FW_WM(tmp, SR);
6346 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6347 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6348 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6351 wm->fbc_en = tmp & DSPFW_FBC_SR_EN;
6352 wm->sr.fbc = _FW_WM(tmp, FBC_SR);
6353 wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR);
6354 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6355 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6356 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6359 wm->hpll_en = tmp & DSPFW_HPLL_SR_EN;
6360 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6361 wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR);
6362 wm->hpll.plane = _FW_WM(tmp, HPLL_SR);
6366 struct vlv_wm_values *wm)
6374 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6376 wm->ddl[pipe].plane[PLANE_CURSOR] =
6378 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6380 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6385 wm->sr.plane = _FW_WM(tmp, SR);
6386 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6387 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6388 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6391 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6392 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6393 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6396 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
6400 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6401 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6404 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6405 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6408 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6409 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6412 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6413 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6414 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6415 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6416 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6417 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6418 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6419 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6420 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6421 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6424 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6425 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6428 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
6429 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6430 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6431 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6432 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6433 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6434 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6443 struct g4x_wm_values *wm = &dev_priv->wm.g4x;
6446 g4x_read_wm_values(dev_priv, wm);
6448 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
6453 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6459 active->cxsr = wm->cxsr;
6460 active->hpll_en = wm->hpll_en;
6461 active->fbc_en = wm->fbc_en;
6463 active->sr = wm->sr;
6464 active->hpll = wm->hpll;
6467 active->wm.plane[plane_id] =
6468 wm->pipe[pipe].plane[plane_id];
6471 if (wm->cxsr && wm->hpll_en)
6473 else if (wm->cxsr)
6479 raw = &crtc_state->wm.g4x.raw[level];
6481 raw->plane[plane_id] = active->wm.plane[plane_id];
6486 raw = &crtc_state->wm.g4x.raw[level];
6495 raw = &crtc_state->wm.g4x.raw[level];
6507 crtc_state->wm.g4x.optimal = *active;
6508 crtc_state->wm.g4x.intermediate = *active;
6513 wm->pipe[pipe].plane[PLANE_PRIMARY],
6514 wm->pipe[pipe].plane[PLANE_CURSOR],
6515 wm->pipe[pipe].plane[PLANE_SPRITE0]);
6520 wm->sr.plane, wm->sr.cursor, wm->sr.fbc);
6523 wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc);
6525 yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en));
6533 mutex_lock(&dev_priv->wm.wm_mutex);
6542 struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal;
6551 &crtc_state->wm.g4x.raw[level];
6554 wm_state->wm.plane[plane_id] = 0;
6560 &crtc_state->wm.g4x.raw[level];
6574 crtc_state->wm.g4x.intermediate =
6575 crtc_state->wm.g4x.optimal;
6576 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6581 mutex_unlock(&dev_priv->wm.wm_mutex);
6586 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
6590 vlv_read_wm_values(dev_priv, wm);
6592 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
6593 wm->level = VLV_WM_LEVEL_PM2;
6600 wm->level = VLV_WM_LEVEL_PM5;
6620 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
6624 wm->level = VLV_WM_LEVEL_DDR_DVFS;
6633 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6635 &crtc_state->wm.vlv.fifo_state;
6642 active->num_levels = wm->level + 1;
6643 active->cxsr = wm->cxsr;
6647 &crtc_state->wm.vlv.raw[level];
6649 active->sr[level].plane = wm->sr.plane;
6650 active->sr[level].cursor = wm->sr.cursor;
6653 active->wm[level].plane[plane_id] =
6654 wm->pipe[pipe].plane[plane_id];
6657 vlv_invert_wm_value(active->wm[level].plane[plane_id],
6667 crtc_state->wm.vlv.optimal = *active;
6668 crtc_state->wm.vlv.intermediate = *active;
6673 wm->pipe[pipe].plane[PLANE_PRIMARY],
6674 wm->pipe[pipe].plane[PLANE_CURSOR],
6675 wm->pipe[pipe].plane[PLANE_SPRITE0],
6676 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6681 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
6689 mutex_lock(&dev_priv->wm.wm_mutex);
6698 struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal;
6700 &crtc_state->wm.vlv.fifo_state;
6709 &crtc_state->wm.vlv.raw[level];
6713 wm_state->wm[level].plane[plane_id] =
6723 crtc_state->wm.vlv.intermediate =
6724 crtc_state->wm.vlv.optimal;
6725 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6730 mutex_unlock(&dev_priv->wm.wm_mutex);
6751 struct ilk_wm_values *hw = &dev_priv->wm.hw;
7651 if ((IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[1] &&
7652 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7653 (!IS_GEN(dev_priv, 5) && dev_priv->wm.pri_latency[0] &&
7654 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {