Lines Matching defs:result
766 * will occur, and a display engine hang could result.
2774 struct intel_wm_level *result)
2779 if (!result->enable)
2782 result->enable = result->pri_val <= max->pri &&
2783 result->spr_val <= max->spr &&
2784 result->cur_val <= max->cur;
2786 ret = result->enable;
2793 if (level == 0 && !result->enable) {
2794 if (result->pri_val > max->pri)
2796 level, result->pri_val, max->pri);
2797 if (result->spr_val > max->spr)
2799 level, result->spr_val, max->spr);
2800 if (result->cur_val > max->cur)
2802 level, result->cur_val, max->cur);
2804 result->pri_val = min_t(u32, result->pri_val, max->pri);
2805 result->spr_val = min_t(u32, result->spr_val, max->spr);
2806 result->cur_val = min_t(u32, result->cur_val, max->cur);
2807 result->enable = true;
2820 struct intel_wm_level *result)
2834 result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
2836 result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
2840 result->spr_val = ilk_compute_spr_wm(crtc_state, sprstate, spr_latency);
2843 result->cur_val = ilk_compute_cur_wm(crtc_state, curstate, cur_latency);
2845 result->enable = true;
3446 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
4255 struct skl_wm_level *result /* out */);
5260 struct skl_wm_level *result /* out */)
5269 result->min_ddb_alloc = U16_MAX;
5332 * Make sure result blocks for higher latency levels are
5365 result->min_ddb_alloc = U16_MAX;
5375 result->plane_res_b = res_blocks;
5376 result->plane_res_l = res_lines;
5378 result->min_ddb_alloc = max(min_ddb_alloc, res_blocks) + 1;
5379 result->plane_en = true;
5392 struct skl_wm_level *result = &levels[level];
5396 wm_params, result_prev, result);
5398 result_prev = result;