Lines Matching defs:pipe

490 	enum pipe pipe = crtc->pipe;
494 switch (pipe) {
514 MISSING_CASE(pipe);
973 enum pipe pipe;
975 for_each_pipe(dev_priv, pipe)
976 trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
980 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
981 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
982 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
987 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) |
988 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
989 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1005 enum pipe pipe;
1007 for_each_pipe(dev_priv, pipe) {
1008 trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm);
1010 I915_WRITE(VLV_DDL(pipe),
1011 (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) |
1012 (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) |
1013 (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) |
1014 (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT));
1030 FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) |
1031 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) |
1032 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA));
1034 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) |
1035 FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) |
1036 FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA));
1042 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1043 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1045 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) |
1046 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE));
1048 FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) |
1049 FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC));
1052 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) |
1053 FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) |
1054 FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) |
1055 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1056 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1057 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1058 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1059 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1060 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1063 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) |
1064 FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC));
1067 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) |
1068 FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) |
1069 FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) |
1070 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) |
1071 FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) |
1072 FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI));
1566 enum pipe pipe = crtc->pipe;
1568 wm->pipe[pipe] = wm_state->wm;
1953 * enabled can wedge the pipe. Hence we only allow cxsr
1956 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
2032 switch (crtc->pipe) {
2176 enum pipe pipe = crtc->pipe;
2178 wm->pipe[pipe] = wm_state->wm[wm->level];
2182 wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2;
2183 wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2;
2184 wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2;
2185 wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2;
3121 /* LP0 watermark maximums depend on this pipe alone */
3141 /* Compute new watermarks for the pipe */
3318 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
3432 enum pipe pipe = intel_crtc->pipe;
3439 results->wm_pipe[pipe] =
3476 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
3487 enum pipe pipe;
3490 for_each_pipe(dev_priv, pipe) {
3491 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
3492 dirty |= WM_DIRTY_PIPE(pipe);
3702 * blocking time, having this enabled can cause full system hangs and/or pipe
3705 * - <= 1 pipe enabled
3910 * If any of the planes on this pipe don't enable wm levels that
3982 new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
3984 new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
4102 enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
4133 * the existing pipe allocation limits should remain unchanged.
4151 * Get allowed DBuf slices for correspondent pipe and platform.
4164 * a number of allowed slices for that pipe multiplied by slice size.
4179 enum pipe pipe = crtc->pipe;
4190 * According to BSpec pipe can share one dbuf slice with another
4191 * pipes or pipe can use multiple dbufs, in both cases we
4212 if (pipe < for_pipe)
4214 else if (pipe == for_pipe)
4300 const enum pipe pipe,
4310 val = I915_READ(CUR_BUF_CFG(pipe));
4315 val = I915_READ(PLANE_CTL(pipe, plane_id));
4324 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4327 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
4328 val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
4345 enum pipe pipe = crtc->pipe;
4349 power_domain = POWER_DOMAIN_PIPE(pipe);
4355 skl_ddb_get_hw_plane_state(dev_priv, pipe,
4603 static u8 compute_dbuf_slices(enum pipe pipe, u8 active_pipes,
4610 return dbuf_slices[i].dbuf_mask[pipe];
4616 * This function finds an entry with same enabled pipe configuration and
4620 static u8 icl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4624 * required calculating "pipe ratio" in order to determine
4625 * if one or two slices can be used for single pipe configurations
4627 * However based on recent info, it should be not "pipe ratio"
4634 return compute_dbuf_slices(pipe, active_pipes, icl_allowed_dbufs);
4637 static u8 tgl_compute_dbuf_slices(enum pipe pipe, u8 active_pipes)
4639 return compute_dbuf_slices(pipe, active_pipes, tgl_allowed_dbufs);
4647 enum pipe pipe = crtc->pipe;
4650 return tgl_compute_dbuf_slices(pipe, active_pipes);
4652 return icl_compute_dbuf_slices(pipe, active_pipes);
4657 return active_pipes & BIT(pipe) ? BIT(DBUF_S1) : 0;
5116 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
5651 enum pipe pipe = plane->pipe;
5664 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
5667 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
5672 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5680 PLANE_BUF_CFG(pipe, plane_id), ddb_y);
5682 PLANE_NV12_BUF_CFG(pipe, plane_id), ddb_uv);
5691 enum pipe pipe = plane->pipe;
5702 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
5705 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5707 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), ddb);
5966 if ((pipe_mask & BIT(crtc->pipe)) == 0)
6047 * deallocate the cursor ddb until the pipe gets disabled. So we must
6109 * weren't otherwise being modified if pipe allocations had to change.
6174 /* 5/6 split only in single pipe config on IVB+ */
6235 enum pipe pipe = crtc->pipe;
6247 val = I915_READ(PLANE_WM(pipe, plane_id, level));
6249 val = I915_READ(CUR_WM(pipe, level));
6258 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
6260 val = I915_READ(CUR_WM_TRANS(pipe));
6293 enum pipe pipe = crtc->pipe;
6300 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
6307 u32 tmp = hw->wm_pipe[pipe];
6346 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6347 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB);
6348 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA);
6354 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB);
6355 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6356 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA);
6368 enum pipe pipe;
6371 for_each_pipe(dev_priv, pipe) {
6372 tmp = I915_READ(VLV_DDL(pipe));
6374 wm->ddl[pipe].plane[PLANE_PRIMARY] =
6376 wm->ddl[pipe].plane[PLANE_CURSOR] =
6378 wm->ddl[pipe].plane[PLANE_SPRITE0] =
6380 wm->ddl[pipe].plane[PLANE_SPRITE1] =
6386 wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB);
6387 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB);
6388 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA);
6391 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB);
6392 wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA);
6393 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA);
6400 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6401 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6404 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF);
6405 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE);
6408 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC);
6409 wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC);
6413 wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
6414 wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
6415 wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8;
6416 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6417 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6418 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6419 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6420 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6421 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6424 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED);
6425 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC);
6429 wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8;
6430 wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
6431 wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8;
6432 wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
6433 wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
6434 wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8;
6455 enum pipe pipe = crtc->pipe;
6468 wm->pipe[pipe].plane[plane_id];
6511 "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n",
6512 pipe_name(pipe),
6513 wm->pipe[pipe].plane[PLANE_PRIMARY],
6514 wm->pipe[pipe].plane[PLANE_CURSOR],
6515 wm->pipe[pipe].plane[PLANE_SPRITE0]);
6537 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6636 enum pipe pipe = crtc->pipe;
6654 wm->pipe[pipe].plane[plane_id];
6671 "Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
6672 pipe_name(pipe),
6673 wm->pipe[pipe].plane[PLANE_PRIMARY],
6674 wm->pipe[pipe].plane[PLANE_CURSOR],
6675 wm->pipe[pipe].plane[PLANE_SPRITE0],
6676 wm->pipe[pipe].plane[PLANE_SPRITE1]);
6693 intel_get_crtc_for_pipe(dev_priv, plane->pipe);
6875 enum pipe pipe;
6877 for_each_pipe(dev_priv, pipe) {
6878 I915_WRITE(DSPCNTR(pipe),
6879 I915_READ(DSPCNTR(pipe)) |
6882 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6883 POSTING_READ(DSPSURF(pipe));
6950 enum pipe pipe;
6966 for_each_pipe(dev_priv, pipe) {
6967 val = I915_READ(TRANS_CHICKEN2(pipe));
6974 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6977 for_each_pipe(dev_priv, pipe) {
6978 I915_WRITE(TRANS_CHICKEN1(pipe),
7271 enum pipe pipe;
7286 for_each_pipe(dev_priv, pipe) {
7287 I915_WRITE(CHICKEN_PIPESL_1(pipe),
7288 I915_READ(CHICKEN_PIPESL_1(pipe)) |