Lines Matching defs:enabled
868 struct intel_crtc *crtc, *enabled = NULL;
872 if (enabled)
874 enabled = crtc;
878 return enabled;
961 * in the actual pixel depth regardless of whether FBC is enabled or not."
1716 * When enabling sprite0 after sprite1 has already been enabled
1719 * cacheline for sprite0 whenever sprite1 is enabled.
1953 * enabled can wedge the pipe. Hence we only allow cxsr
1954 * with exactly one enabled primary/sprite plane.
2303 /* Turn off self refresh if both pipes are enabled */
2336 struct intel_crtc *crtc, *enabled = NULL;
2362 enabled = crtc;
2389 if (enabled == NULL)
2390 enabled = crtc;
2392 enabled = NULL;
2402 if (IS_I915GM(dev_priv) && enabled) {
2405 obj = intel_fb_obj(enabled->base.primary->state->fb);
2409 enabled = NULL;
2421 if (HAS_FW_BLC(dev_priv) && enabled) {
2425 &enabled->config->hw.adjusted_mode;
2427 enabled->base.primary->state->fb;
2430 int hdisplay = enabled->config->pipe_src_w;
2469 if (enabled)
2705 /* if sprites aren't enabled, sprites get nothing */
3349 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
3351 * FIXME this is racy. FBC might get enabled later.
3353 * enabled sometime later.
3446 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
3702 * blocking time, having this enabled can cause full system hangs and/or pipe
3705 * - <= 1 pipe enabled
3893 /* Skip this plane if it's not enabled */
3897 /* Find the highest enabled wm level for this plane */
4029 * and mask(i.e if slice size is 1024 and second slice is enabled
4616 * This function finds an entry with same enabled pipe configuration and
4986 * all levels as "enabled." Go back now and disable the ones
5002 * "All the watermarks at this level for all enabled
5003 * planes must be enabled before the level will be used."
5600 * enabled, so make sure all other planes are set as disabled.
6311 * enabled, and LP1+ watermaks as disabled since
6324 * should be marked as enabled but zeroed,
7058 * TODO: this bit should only be enabled when really needed, then