Lines Matching defs:crtc
487 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
490 enum pipe pipe = crtc->pipe;
847 static bool intel_crtc_active(struct intel_crtc *crtc)
855 * We can ditch the crtc->primary->state->fb check as soon as we can
859 * crtc->state->active once we have proper CRTC states wired up
862 return crtc->active && crtc->base.primary->state->fb &&
863 crtc->config->hw.adjusted_mode.crtc_clock;
868 struct intel_crtc *crtc, *enabled = NULL;
870 for_each_intel_crtc(&dev_priv->drm, crtc) {
871 if (intel_crtc_active(crtc)) {
874 enabled = crtc;
884 struct intel_crtc *crtc;
900 crtc = single_enabled_crtc(dev_priv);
901 if (crtc) {
903 &crtc->config->hw.adjusted_mode;
905 crtc->base.primary->state->fb;
1196 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1212 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1236 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1317 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1328 static void g4x_invalidate_wms(struct intel_crtc *crtc,
1334 for_each_plane_id_on_crtc(crtc, plane_id)
1372 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1389 if (new_plane_state->hw.crtc != &crtc->base &&
1390 old_plane_state->hw.crtc != &crtc->base)
1405 for_each_plane_id_on_crtc(crtc, plane_id)
1437 g4x_invalidate_wms(crtc, wm_state, level);
1453 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
1454 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1460 intel_atomic_get_old_crtc_state(intel_state, crtc);
1478 for_each_plane_id_on_crtc(crtc, plane_id) {
1535 struct intel_crtc *crtc;
1542 for_each_intel_crtc(&dev_priv->drm, crtc) {
1543 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1545 if (!crtc->active)
1564 for_each_intel_crtc(&dev_priv->drm, crtc) {
1565 const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x;
1566 enum pipe pipe = crtc->pipe;
1569 if (crtc->active && wm->cxsr)
1571 if (crtc->active && wm->hpll_en)
1598 struct intel_crtc *crtc)
1600 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1602 intel_atomic_get_new_crtc_state(state, crtc);
1605 crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
1611 struct intel_crtc *crtc)
1613 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1615 intel_atomic_get_new_crtc_state(state, crtc);
1621 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
1702 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1703 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1737 for_each_plane_id_on_crtc(crtc, plane_id) {
1758 for_each_plane_id_on_crtc(crtc, plane_id) {
1784 static void vlv_invalidate_wms(struct intel_crtc *crtc,
1787 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1792 for_each_plane_id_on_crtc(crtc, plane_id)
1815 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1833 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1892 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1893 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1912 if (new_plane_state->hw.crtc != &crtc->base &&
1913 old_plane_state->hw.crtc != &crtc->base)
1935 intel_atomic_get_old_crtc_state(state, crtc);
1956 wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1;
1965 for_each_plane_id_on_crtc(crtc, plane_id) {
1989 vlv_invalidate_wms(crtc, wm_state, level);
1998 struct intel_crtc *crtc)
2000 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2003 intel_atomic_get_new_crtc_state(state, crtc);
2019 trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size);
2032 switch (crtc->pipe) {
2097 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
2103 intel_atomic_get_old_crtc_state(intel_state, crtc);
2121 for_each_plane_id_on_crtc(crtc, plane_id) {
2133 vlv_invalidate_wms(crtc, intermediate, level);
2149 struct intel_crtc *crtc;
2155 for_each_intel_crtc(&dev_priv->drm, crtc) {
2156 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2158 if (!crtc->active)
2174 for_each_intel_crtc(&dev_priv->drm, crtc) {
2175 const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv;
2176 enum pipe pipe = crtc->pipe;
2179 if (crtc->active && wm->cxsr)
2223 struct intel_crtc *crtc)
2225 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2227 intel_atomic_get_new_crtc_state(state, crtc);
2230 crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
2236 struct intel_crtc *crtc)
2238 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2240 intel_atomic_get_new_crtc_state(state, crtc);
2246 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
2254 struct intel_crtc *crtc;
2260 crtc = single_enabled_crtc(dev_priv);
2261 if (crtc) {
2265 &crtc->config->hw.adjusted_mode;
2267 crtc->base.primary->state->fb;
2270 int hdisplay = crtc->config->pipe_src_w;
2286 crtc->base.cursor->state->crtc_w, 4,
2336 struct intel_crtc *crtc, *enabled = NULL;
2346 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_A);
2347 if (intel_crtc_active(crtc)) {
2349 &crtc->config->hw.adjusted_mode;
2351 crtc->base.primary->state->fb;
2362 enabled = crtc;
2373 crtc = intel_get_crtc_for_plane(dev_priv, PLANE_B);
2374 if (intel_crtc_active(crtc)) {
2376 &crtc->config->hw.adjusted_mode;
2378 crtc->base.primary->state->fb;
2390 enabled = crtc;
2476 struct intel_crtc *crtc;
2481 crtc = single_enabled_crtc(dev_priv);
2482 if (crtc == NULL)
2485 adjusted_mode = &crtc->config->hw.adjusted_mode;
2814 const struct intel_crtc *crtc,
3144 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
3145 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3185 ilk_compute_wm_level(dev_priv, crtc, 0, crtc_state,
3196 ilk_compute_wm_level(dev_priv, crtc, level, crtc_state,
3220 struct intel_crtc *intel_crtc = to_intel_crtc(newstate->uapi.crtc);
3874 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3875 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3923 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3929 for_each_plane_id_on_crtc(crtc, plane_id) {
3944 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3945 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3967 struct intel_crtc *crtc;
3973 for_each_new_intel_crtc_in_state(state, crtc,
3982 new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
3984 new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
4010 for_each_new_intel_crtc_in_state(state, crtc,
4015 * We store use_sagv_wm in the crtc state rather than relying on
4099 struct drm_crtc *for_crtc = crtc_state->uapi.crtc;
4100 const struct intel_crtc *crtc;
4136 * grab _all_ crtc locks, including the one we currently hold.
4176 for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
4179 enum pipe pipe = crtc->pipe;
4261 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4339 void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
4343 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4345 enum pipe pipe = crtc->pipe;
4354 for_each_plane_id_on_crtc(crtc, plane_id)
4383 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
4645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4646 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4647 enum pipe pipe = crtc->pipe;
4796 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4797 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4880 for_each_plane_id_on_crtc(crtc, plane_id) {
4917 for_each_plane_id_on_crtc(crtc, plane_id) {
4956 for_each_plane_id_on_crtc(crtc, plane_id) {
4990 for_each_plane_id_on_crtc(crtc, plane_id) {
5027 for_each_plane_id_on_crtc(crtc, plane_id) {
5083 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5106 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5133 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5134 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5262 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5387 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5406 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5420 struct drm_device *dev = crtc_state->uapi.crtc->dev;
5483 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
5484 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5554 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5592 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
5764 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
5765 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
5768 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5796 struct intel_crtc *crtc;
5799 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5837 struct intel_crtc *crtc;
5843 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5850 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5867 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5961 struct intel_crtc *crtc;
5963 for_each_intel_crtc(&dev_priv->drm, crtc) {
5966 if ((pipe_mask & BIT(crtc->pipe)) == 0)
5969 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5982 struct intel_crtc *crtc;
5998 for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6057 struct intel_crtc *crtc)
6059 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6061 intel_atomic_get_old_crtc_state(state, crtc);
6063 intel_atomic_get_new_crtc_state(state, crtc);
6066 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
6097 struct intel_crtc *crtc;
6111 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6131 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6133 ret = skl_wm_add_affected_planes(state, crtc);
6146 struct intel_crtc *crtc;
6149 for_each_intel_crtc(&dev_priv->drm, crtc) {
6150 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
6194 struct intel_crtc *crtc)
6196 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6198 intel_atomic_get_new_crtc_state(state, crtc);
6201 crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
6207 struct intel_crtc *crtc)
6209 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6211 intel_atomic_get_new_crtc_state(state, crtc);
6217 crtc->wm.active.ilk = crtc_state->wm.ilk.optimal;
6231 void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
6234 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6235 enum pipe pipe = crtc->pipe;
6242 for_each_plane_id_on_crtc(crtc, plane_id) {
6265 if (!crtc->active)
6271 struct intel_crtc *crtc;
6274 for_each_intel_crtc(&dev_priv->drm, crtc) {
6275 crtc_state = to_intel_crtc_state(crtc->base.state);
6277 skl_pipe_wm_get_hw_state(crtc, &crtc_state->wm.skl.optimal);
6286 static void ilk_pipe_wm_get_hw_state(struct intel_crtc *crtc)
6288 struct drm_device *dev = crtc->base.dev;
6291 struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
6293 enum pipe pipe = crtc->pipe;
6304 active->pipe_enabled = crtc->active;
6331 crtc->wm.active.ilk = *active;
6444 struct intel_crtc *crtc;
6450 for_each_intel_crtc(&dev_priv->drm, crtc) {
6452 to_intel_crtc_state(crtc->base.state);
6453 struct g4x_wm_state *active = &crtc->wm.active.g4x;
6455 enum pipe pipe = crtc->pipe;
6466 for_each_plane_id_on_crtc(crtc, plane_id) {
6480 for_each_plane_id_on_crtc(crtc, plane_id)
6502 for_each_plane_id_on_crtc(crtc, plane_id)
6531 struct intel_crtc *crtc;
6536 struct intel_crtc *crtc =
6539 to_intel_crtc_state(crtc->base.state);
6570 for_each_intel_crtc(&dev_priv->drm, crtc) {
6572 to_intel_crtc_state(crtc->base.state);
6576 crtc->wm.active.g4x = crtc_state->wm.g4x.optimal;
6587 struct intel_crtc *crtc;
6630 for_each_intel_crtc(&dev_priv->drm, crtc) {
6632 to_intel_crtc_state(crtc->base.state);
6633 struct vlv_wm_state *active = &crtc->wm.active.vlv;
6636 enum pipe pipe = crtc->pipe;
6652 for_each_plane_id_on_crtc(crtc, plane_id) {
6662 for_each_plane_id_on_crtc(crtc, plane_id)
6665 vlv_invalidate_wms(crtc, active, level);
6687 struct intel_crtc *crtc;
6692 struct intel_crtc *crtc =
6695 to_intel_crtc_state(crtc->base.state);
6719 for_each_intel_crtc(&dev_priv->drm, crtc) {
6721 to_intel_crtc_state(crtc->base.state);
6725 crtc->wm.active.vlv = crtc_state->wm.vlv.optimal;
6752 struct intel_crtc *crtc;
6756 for_each_intel_crtc(&dev_priv->drm, crtc)
6757 ilk_pipe_wm_get_hw_state(crtc);
6782 * @crtc: the #intel_crtc on which to compute the WM
6813 void intel_update_watermarks(struct intel_crtc *crtc)
6815 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6818 dev_priv->display.update_wm(crtc);