Lines Matching defs:clock
661 * to account for TLB misses and clock crossings.
708 * to account for TLB misses and clock crossings.
751 * @pixel_rate: pixel clock
762 * As the pixel clock runs, the FIFO will be drained at a rate that depends
776 * Note: we need to make sure we don't overflow for various clock &
853 * as Haswell has gained clock readout/fastboot support.
907 int clock = adjusted_mode->crtc_clock;
910 wm = intel_calculate_wm(clock, &pnv_display_wm,
920 wm = intel_calculate_wm(clock, &pnv_cursor_wm,
929 wm = intel_calculate_wm(clock, &pnv_display_hplloff_wm,
938 wm = intel_calculate_wm(clock, &pnv_cursor_hplloff_wm,
1141 unsigned int clock, htotal, cpp, width, wm;
1166 clock = adjusted_mode->crtc_clock;
1172 wm = intel_wm_method2(clock, htotal, width, cpp, latency);
1175 wm = intel_wm_method1(clock, cpp, latency);
1179 small = intel_wm_method1(clock, cpp, latency);
1180 large = intel_wm_method2(clock, htotal, width, cpp, latency);
1665 unsigned int clock, htotal, cpp, width, wm;
1674 clock = adjusted_mode->crtc_clock;
1687 wm = vlv_wm_method2(clock, htotal, width, cpp,
2268 int clock = adjusted_mode->crtc_clock;
2274 entries = intel_wm_method2(clock, htotal,
2285 entries = intel_wm_method2(clock, htotal,
2428 int clock = adjusted_mode->crtc_clock;
2439 entries = intel_wm_method2(clock, htotal, hdisplay, cpp,
3699 * SAGV dynamically adjusts the system agent voltage and clock frequencies
6808 * and include an extra 2 entries to account for clock crossings.
6866 * On Ibex Peak and Cougar Point, we need to disable clock
6954 * On Ibex Peak and Cougar Point, we need to disable clock
7009 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7100 * Wait at least 100 clocks before re-enabling clock gating.
7317 * clock gating.
7417 * Disabling L3 clock gating- MMIO 940c[25] = 1
7424 * Disable clock gating on th GCFG unit to prevent a delay
7570 "No clock gating settings or workarounds applied.\n");
7574 * intel_init_clock_gating_hooks - setup the clock gating hooks