Lines Matching defs:reg
182 u32 reg;
185 #define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
189 static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
191 return reg.reg;
199 static inline bool i915_mmio_reg_valid(i915_reg_t reg)
201 return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
251 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
252 INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
254 #define _TRANS2(tran, reg) (INTEL_INFO(dev_priv)->trans_offsets[(tran)] - \
255 INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
257 #define _MMIO_TRANS2(tran, reg) _MMIO(_TRANS2(tran, reg))
258 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
259 INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
1739 #define _BXT_PHY(phy, reg) \
1740 _MMIO(BXT_PHY_BASE(phy) - _BXT_PHY0_BASE + (reg))
2814 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */
4450 #define _PSR_ADJ(tran, reg) (_TRANS2(tran, reg) - dev_priv->hsw_psr_mmio_adjust)
4999 #define _MMIO_PPS(pps_idx, reg) _MMIO(dev_priv->pps_mmio_base - \
5000 PPS_BASE + (reg) + \
6856 #define _MMIO_CHV_SPCSC(plane_id, reg) \
6857 _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg))
9329 #define GEN7_PARITY_ERROR_ROW(reg) \
9330 (((reg) & GEN7_L3CDERRST1_ROW_MASK) >> 14)
9331 #define GEN7_PARITY_ERROR_BANK(reg) \
9332 (((reg) & GEN7_L3CDERRST1_BANK_MASK) >> 11)
9333 #define GEN7_PARITY_ERROR_SUBBANK(reg) \
9334 (((reg) & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)