Lines Matching defs:DPLL
3419 #define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C)
3502 * Selects the phase for the 10X DPLL clock for the PCIe
3534 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
3540 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
4900 * the DPLL semantics change when the LVDS is assigned to that pipe.
4941 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
10221 /* DPLL control1 */
10236 /* DPLL control2 */
10244 /* DPLL Status */
10248 /* DPLL cfg */