Lines Matching refs:iir
204 i915_reg_t iir, i915_reg_t ier)
212 intel_uncore_write(uncore, iir, 0xffffffff);
213 intel_uncore_posting_read(uncore, iir);
214 intel_uncore_write(uncore, iir, 0xffffffff);
215 intel_uncore_posting_read(uncore, iir);
270 i915_reg_t iir)
272 gen3_assert_iir_is_zero(uncore, iir);
1304 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1342 if (iir & iir_bit)
1370 u16 iir, u32 pipe_stats[I915_MAX_PIPES])
1387 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1406 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1411 u32 iir, u32 pipe_stats[I915_MAX_PIPES])
1430 if (blc_event || (iir & I915_ASLE_INTERRUPT))
1534 u32 iir, gt_iir, pm_iir;
1541 iir = I915_READ(VLV_IIR);
1543 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1570 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1574 * signalled in iir */
1575 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1577 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1585 if (iir)
1586 I915_WRITE(VLV_IIR, iir);
1619 u32 master_ctl, iir;
1625 iir = I915_READ(VLV_IIR);
1627 if (master_ctl == 0 && iir == 0)
1651 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1655 * signalled in iir */
1656 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
1658 if (iir & (I915_LPE_PIPE_A_INTERRUPT |
1667 if (iir)
1668 I915_WRITE(VLV_IIR, iir);
2057 /* disable master interrupt before clearing iir */
2128 static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2131 u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
2132 u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
2162 "Unexpected DE HPD interrupt 0x%08x\n", iir);
2209 gen8_de_misc_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
2213 if (iir & GEN8_DE_MISC_GSE) {
2218 if (iir & GEN8_DE_EDP_PSR) {
2244 u32 iir;
2248 iir = I915_READ(GEN8_DE_MISC_IIR);
2249 if (iir) {
2250 I915_WRITE(GEN8_DE_MISC_IIR, iir);
2252 gen8_de_misc_irq_handler(dev_priv, iir);
2260 iir = I915_READ(GEN11_DE_HPD_IIR);
2261 if (iir) {
2262 I915_WRITE(GEN11_DE_HPD_IIR, iir);
2264 gen11_hpd_irq_handler(dev_priv, iir);
2272 iir = I915_READ(GEN8_DE_PORT_IIR);
2273 if (iir) {
2277 I915_WRITE(GEN8_DE_PORT_IIR, iir);
2280 if (iir & gen8_de_port_aux_mask(dev_priv)) {
2286 tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
2292 tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
2299 if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
2319 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2320 if (!iir) {
2327 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2329 if (iir & GEN8_PIPE_VBLANK)
2332 if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
2335 if (iir & GEN8_PIPE_FIFO_UNDERRUN)
2338 fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
2353 iir = I915_READ(SDEIIR);
2354 if (iir) {
2355 I915_WRITE(SDEIIR, iir);
2359 icp_irq_handler(dev_priv, iir);
2361 spt_irq_handler(dev_priv, iir);
2363 cpt_irq_handler(dev_priv, iir);
2429 u32 iir;
2434 iir = raw_reg_read(regs, GEN11_GU_MISC_IIR);
2435 if (likely(iir))
2436 raw_reg_write(regs, GEN11_GU_MISC_IIR, iir);
2438 return iir;
2442 gen11_gu_misc_irq_handler(struct intel_gt *gt, const u32 iir)
2444 if (iir & GEN11_GU_MISC_GSE)
3665 u16 iir;
3667 iir = intel_uncore_read16(&dev_priv->uncore, GEN2_IIR);
3668 if (iir == 0)
3674 * signalled in iir */
3675 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3677 if (iir & I915_MASTER_ERROR_INTERRUPT)
3680 intel_uncore_write16(&dev_priv->uncore, GEN2_IIR, iir);
3682 if (iir & I915_USER_INTERRUPT)
3685 if (iir & I915_MASTER_ERROR_INTERRUPT)
3688 i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3766 u32 iir;
3768 iir = I915_READ(GEN2_IIR);
3769 if (iir == 0)
3775 iir & I915_DISPLAY_PORT_INTERRUPT)
3779 * signalled in iir */
3780 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3782 if (iir & I915_MASTER_ERROR_INTERRUPT)
3785 I915_WRITE(GEN2_IIR, iir);
3787 if (iir & I915_USER_INTERRUPT)
3790 if (iir & I915_MASTER_ERROR_INTERRUPT)
3796 i915_pipestat_irq_handler(dev_priv, iir, pipe_stats);
3909 u32 iir;
3911 iir = I915_READ(GEN2_IIR);
3912 if (iir == 0)
3917 if (iir & I915_DISPLAY_PORT_INTERRUPT)
3921 * signalled in iir */
3922 i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats);
3924 if (iir & I915_MASTER_ERROR_INTERRUPT)
3927 I915_WRITE(GEN2_IIR, iir);
3929 if (iir & I915_USER_INTERRUPT)
3932 if (iir & I915_BSD_USER_INTERRUPT)
3935 if (iir & I915_MASTER_ERROR_INTERRUPT)
3941 i965_pipestat_irq_handler(dev_priv, iir, pipe_stats);