Lines Matching defs:pipe
196 intel_handle_vblank(struct drm_i915_private *dev_priv, enum pipe pipe)
198 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
390 * bdw_update_pipe_irq - update DE pipe interrupt
392 * @pipe: pipe whose interrupt to update
397 enum pipe pipe,
410 new_val = dev_priv->de_irq_mask[pipe];
414 if (new_val != dev_priv->de_irq_mask[pipe]) {
415 dev_priv->de_irq_mask[pipe] = new_val;
416 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
417 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
447 enum pipe pipe)
449 u32 status_mask = dev_priv->pipestat_irq_mask[pipe];
458 * On pipe A we don't support the PSR interrupt yet,
459 * on pipe B and C the same bit MBZ.
465 * On pipe B and C we don't support the PSR interrupt yet, on pipe
484 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
485 pipe_name(pipe), enable_mask, status_mask);
491 enum pipe pipe, u32 status_mask)
493 i915_reg_t reg = PIPESTAT(pipe);
497 "pipe %c: status_mask=0x%x\n",
498 pipe_name(pipe), status_mask);
503 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == status_mask)
506 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
507 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
514 enum pipe pipe, u32 status_mask)
516 i915_reg_t reg = PIPESTAT(pipe);
520 "pipe %c: status_mask=0x%x\n",
521 pipe_name(pipe), status_mask);
526 if ((dev_priv->pipestat_irq_mask[pipe] & status_mask) == 0)
529 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
530 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
614 * we use as a pipe index
621 enum pipe pipe = to_intel_crtc(crtc)->pipe;
652 high_frame = PIPEFRAME(pipe);
653 low_frame = PIPEFRAMEPIXEL(pipe);
685 enum pipe pipe = to_intel_crtc(crtc)->pipe;
687 return I915_READ(PIPE_FRMCOUNT_G4X(pipe));
691 * On certain encoders on certain platforms, pipe
719 * pipe frame time stamp. The time stamp value
723 PIPE_FRMTMSTMP(crtc->pipe));
732 PIPE_FRMTMSTMP(crtc->pipe));
753 enum pipe pipe = crtc->pipe;
770 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
772 position = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
791 temp = intel_de_read_fw(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
815 enum pipe pipe = crtc->pipe;
826 "pipe %c\n", pipe_name(pipe));
865 position = (intel_de_read_fw(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
1207 enum pipe pipe,
1212 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
1242 enum pipe pipe,
1250 enum pipe pipe)
1252 display_pipe_crc_irq_handler(dev_priv, pipe,
1253 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1258 enum pipe pipe)
1260 display_pipe_crc_irq_handler(dev_priv, pipe,
1261 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1262 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1263 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1264 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1265 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
1269 enum pipe pipe)
1274 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1279 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1283 display_pipe_crc_irq_handler(dev_priv, pipe,
1284 I915_READ(PIPE_CRC_RES_RED(pipe)),
1285 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1286 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1292 enum pipe pipe;
1294 for_each_pipe(dev_priv, pipe) {
1295 I915_WRITE(PIPESTAT(pipe),
1299 dev_priv->pipestat_irq_mask[pipe] = 0;
1306 enum pipe pipe;
1315 for_each_pipe(dev_priv, pipe) {
1330 switch (pipe) {
1343 status_mask |= dev_priv->pipestat_irq_mask[pipe];
1348 reg = PIPESTAT(pipe);
1349 pipe_stats[pipe] = I915_READ(reg) & status_mask;
1350 enable_mask = i915_pipestat_enable_mask(dev_priv, pipe);
1356 * edge in the ISR pipe event bit if we don't clear
1361 if (pipe_stats[pipe]) {
1362 I915_WRITE(reg, pipe_stats[pipe]);
1372 enum pipe pipe;
1374 for_each_pipe(dev_priv, pipe) {
1375 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1376 intel_handle_vblank(dev_priv, pipe);
1378 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1379 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1381 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1382 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1390 enum pipe pipe;
1392 for_each_pipe(dev_priv, pipe) {
1393 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
1394 intel_handle_vblank(dev_priv, pipe);
1396 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1399 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1400 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1402 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1403 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1414 enum pipe pipe;
1416 for_each_pipe(dev_priv, pipe) {
1417 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1418 intel_handle_vblank(dev_priv, pipe);
1420 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
1423 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1424 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1426 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1427 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1440 enum pipe pipe;
1442 for_each_pipe(dev_priv, pipe) {
1443 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS)
1444 intel_handle_vblank(dev_priv, pipe);
1446 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1447 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1449 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1450 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1718 enum pipe pipe;
1746 for_each_pipe(dev_priv, pipe)
1747 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1748 pipe_name(pipe),
1749 I915_READ(FDI_RX_IIR(pipe)));
1769 enum pipe pipe;
1774 for_each_pipe(dev_priv, pipe) {
1775 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1776 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1778 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1780 ivb_pipe_crc_irq_handler(dev_priv, pipe);
1782 hsw_pipe_crc_irq_handler(dev_priv, pipe);
1792 enum pipe pipe;
1797 for_each_pipe(dev_priv, pipe)
1798 if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
1799 intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
1806 enum pipe pipe;
1831 for_each_pipe(dev_priv, pipe)
1832 drm_dbg(&dev_priv->drm, " pipe %c FDI IIR: 0x%08x\n",
1833 pipe_name(pipe),
1834 I915_READ(FDI_RX_IIR(pipe)));
1952 enum pipe pipe;
1967 for_each_pipe(dev_priv, pipe) {
1968 if (de_iir & DE_PIPE_VBLANK(pipe))
1969 intel_handle_vblank(dev_priv, pipe);
1971 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
1972 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
1974 if (de_iir & DE_PIPE_CRC_DONE(pipe))
1975 i9xx_pipe_crc_irq_handler(dev_priv, pipe);
1998 enum pipe pipe;
2020 for_each_pipe(dev_priv, pipe) {
2021 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
2022 intel_handle_vblank(dev_priv, pipe);
2245 enum pipe pipe;
2313 for_each_pipe(dev_priv, pipe) {
2316 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2319 iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
2327 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
2330 intel_handle_vblank(dev_priv, pipe);
2333 hsw_pipe_crc_irq_handler(dev_priv, pipe);
2336 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
2341 "Fault errors on pipe %c: 0x%08x\n",
2342 pipe_name(pipe),
2568 * we use as a pipe index
2573 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2577 i915_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2602 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2606 i915_enable_pipestat(dev_priv, pipe,
2616 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2619 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2637 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2641 bdw_enable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2654 * we use as a pipe index
2659 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2663 i915_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_STATUS);
2680 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2684 i915_disable_pipestat(dev_priv, pipe,
2692 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2695 DE_PIPE_VBLANK_IVB(pipe) : DE_PIPE_VBLANK(pipe);
2705 enum pipe pipe = to_intel_crtc(crtc)->pipe;
2709 bdw_disable_pipe_irq(dev_priv, pipe, GEN8_PIPE_VBLANK);
2768 enum pipe pipe;
2773 for_each_pipe(dev_priv, pipe)
2774 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
2829 enum pipe pipe;
2838 for_each_pipe(dev_priv, pipe)
2840 POWER_DOMAIN_PIPE(pipe)))
2841 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2854 enum pipe pipe;
2878 for_each_pipe(dev_priv, pipe)
2880 POWER_DOMAIN_PIPE(pipe)))
2881 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
2921 enum pipe pipe;
2930 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2931 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
2932 dev_priv->de_irq_mask[pipe],
2933 ~dev_priv->de_irq_mask[pipe] | extra_ier);
2942 enum pipe pipe;
2951 for_each_pipe_masked(dev_priv, pipe, pipe_mask)
2952 GEN8_IRQ_RESET_NDX(uncore, DE_PIPE, pipe);
3395 enum pipe pipe;
3428 for_each_pipe(dev_priv, pipe) {
3429 dev_priv->de_irq_mask[pipe] = ~de_pipe_masked;
3432 POWER_DOMAIN_PIPE(pipe)))
3433 GEN8_IRQ_INIT_NDX(uncore, DE_PIPE, pipe,
3434 dev_priv->de_irq_mask[pipe],