Lines Matching defs:bits
293 u32 bits)
298 drm_WARN_ON(&dev_priv->drm, bits & ~mask);
302 val |= bits;
309 * @mask: bits to update
310 * @bits: bits to enable
311 * NOTE: the HPD enable bits are modified both inside and outside
313 * interfer, these bits are protected by a spinlock. Since this
320 u32 bits)
323 i915_hotplug_interrupt_update_locked(dev_priv, mask, bits);
330 * @interrupt_mask: mask of interrupt bits to update
331 * @enabled_irq_mask: mask of interrupt bits to enable
360 * @interrupt_mask: mask of interrupt bits to update
361 * @enabled_irq_mask: mask of interrupt bits to enable
393 * @interrupt_mask: mask of interrupt bits to update
394 * @enabled_irq_mask: mask of interrupt bits to enable
424 * @interrupt_mask: mask of interrupt bits to update
425 * @enabled_irq_mask: mask of interrupt bits to enable
1320 * PIPESTAT bits get signalled even when the interrupt is
1321 * disabled with the mask bits, and some of the status bits do
1355 * Toggle the enable bits to make sure we get an
1357 * all the enabled status bits. Otherwise the edge
1471 * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port
1476 * bits can itself generate a new hotplug interrupt :(
1559 * bits this time around.
1573 /* Call regardless, as some status bits might not be
1643 * bits this time around.
1654 /* Call regardless, as some status bits might not be
2040 * 3 - Clear the Interrupt Identity bits (IIR).
2041 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2475 * for the display related bits.
3009 * The pulse duration bits are reserved on LPT+.
3192 * The pulse duration bits are reserved on HSW+.
3589 * Toggle all EMR bits to make sure we get an edge
3591 * all the EIR bits. Otherwise the edge triggered
3593 * is still pending. Also some EIR bits can't be
3627 * Toggle all EMR bits to make sure we get an edge
3629 * all the EIR bits. Otherwise the edge triggered
3631 * is still pending. Also some EIR bits can't be
3673 /* Call regardless, as some status bits might not be
3778 /* Call regardless, as some status bits might not be
3875 /* Note HDMI and DP share hotplug bits */
3876 /* enable bits are the same for all generations */
3920 /* Call regardless, as some status bits might not be
3969 /* pre-gen11 the guc irqs bits are in the upper 16 bits of the pm reg */