Lines Matching defs:value
17 int value;
27 value = i915->drm.pdev->device;
30 value = i915->drm.pdev->revision;
33 value = i915->ggtt.num_fences;
36 value = !!i915->overlay;
39 value = !!intel_engine_lookup_user(i915,
43 value = !!intel_engine_lookup_user(i915,
47 value = !!intel_engine_lookup_user(i915,
51 value = !!intel_engine_lookup_user(i915,
55 value = HAS_LLC(i915);
58 value = HAS_WT(i915);
61 value = INTEL_PPGTT(i915);
64 value = !!(i915->caps.scheduler & I915_SCHEDULER_CAP_SEMAPHORES);
67 value = HAS_SECURE_BATCHES(i915) && capable(CAP_SYS_ADMIN);
70 value = i915_cmd_parser_get_version(i915);
73 value = intel_sseu_subslice_total(sseu);
74 if (!value)
78 value = sseu->eu_total;
79 if (!value)
83 value = i915->params.enable_hangcheck &&
85 if (value && intel_has_reset_engine(&i915->gt))
86 value = 2;
89 value = 0;
92 value = HAS_POOLED_EU(i915);
95 value = sseu->min_eu_in_pool;
98 value = intel_huc_check_status(&i915->gt.uc.huc);
99 if (value < 0)
100 return value;
104 * earlier versions as 0, in effect their value is undefined as
107 value = i915_gem_mmap_gtt_version();
110 value = i915->caps.scheduler;
138 * features this value needs to be provided from
141 value = 1;
144 value = intel_engines_has_context_isolation(i915);
147 value = sseu->slice_mask;
148 if (!value)
152 value = sseu->subslice_mask[0];
153 if (!value)
157 value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;
160 value = INTEL_INFO(i915)->has_coherent_ggtt;
163 value = i915_perf_ioctl_version();
170 if (put_user(value, param->value))