Lines Matching defs:vgpu
38 void populate_pvinfo_page(struct intel_vgpu *vgpu)
40 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
42 vgpu_vreg64_t(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
43 vgpu_vreg_t(vgpu, vgtif_reg(version_major)) = 1;
44 vgpu_vreg_t(vgpu, vgtif_reg(version_minor)) = 0;
45 vgpu_vreg_t(vgpu, vgtif_reg(display_ready)) = 0;
46 vgpu_vreg_t(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
48 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) = VGT_CAPS_FULL_PPGTT;
49 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HWSP_EMULATION;
50 vgpu_vreg_t(vgpu, vgtif_reg(vgt_caps)) |= VGT_CAPS_HUGE_GTT;
52 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
53 vgpu_aperture_gmadr_base(vgpu);
54 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
55 vgpu_aperture_sz(vgpu);
56 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
57 vgpu_hidden_gmadr_base(vgpu);
58 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
59 vgpu_hidden_sz(vgpu);
61 vgpu_vreg_t(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
63 vgpu_vreg_t(vgpu, vgtif_reg(cursor_x_hot)) = UINT_MAX;
64 vgpu_vreg_t(vgpu, vgtif_reg(cursor_y_hot)) = UINT_MAX;
66 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
68 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
70 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
71 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
209 * @vgpu: virtual GPU
214 void intel_gvt_activate_vgpu(struct intel_vgpu *vgpu)
216 mutex_lock(&vgpu->vgpu_lock);
217 vgpu->active = true;
218 mutex_unlock(&vgpu->vgpu_lock);
223 * @vgpu: virtual GPU
229 void intel_gvt_deactivate_vgpu(struct intel_vgpu *vgpu)
231 mutex_lock(&vgpu->vgpu_lock);
233 vgpu->active = false;
235 if (atomic_read(&vgpu->submission.running_workload_num)) {
236 mutex_unlock(&vgpu->vgpu_lock);
237 intel_gvt_wait_vgpu_idle(vgpu);
238 mutex_lock(&vgpu->vgpu_lock);
241 intel_vgpu_stop_schedule(vgpu);
243 mutex_unlock(&vgpu->vgpu_lock);
248 * @vgpu: virtual GPU
255 void intel_gvt_release_vgpu(struct intel_vgpu *vgpu)
257 intel_gvt_deactivate_vgpu(vgpu);
259 mutex_lock(&vgpu->vgpu_lock);
260 vgpu->d3_entered = false;
261 intel_vgpu_clean_workloads(vgpu, ALL_ENGINES);
262 intel_vgpu_dmabuf_cleanup(vgpu);
263 mutex_unlock(&vgpu->vgpu_lock);
268 * @vgpu: virtual GPU
273 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
275 struct intel_gvt *gvt = vgpu->gvt;
278 drm_WARN(&i915->drm, vgpu->active, "vGPU is still active!\n");
282 * service if no active vgpu.
285 idr_remove(&gvt->vgpu_idr, vgpu->id);
288 mutex_lock(&vgpu->vgpu_lock);
289 intel_gvt_debugfs_remove_vgpu(vgpu);
290 intel_vgpu_clean_sched_policy(vgpu);
291 intel_vgpu_clean_submission(vgpu);
292 intel_vgpu_clean_display(vgpu);
293 intel_vgpu_clean_opregion(vgpu);
294 intel_vgpu_reset_ggtt(vgpu, true);
295 intel_vgpu_clean_gtt(vgpu);
296 intel_gvt_hypervisor_detach_vgpu(vgpu);
297 intel_vgpu_free_resource(vgpu);
298 intel_vgpu_clean_mmio(vgpu);
299 intel_vgpu_dmabuf_cleanup(vgpu);
300 mutex_unlock(&vgpu->vgpu_lock);
308 vfree(vgpu);
324 struct intel_vgpu *vgpu;
328 vgpu = vzalloc(sizeof(*vgpu));
329 if (!vgpu)
332 vgpu->id = IDLE_VGPU_IDR;
333 vgpu->gvt = gvt;
334 mutex_init(&vgpu->vgpu_lock);
337 INIT_LIST_HEAD(&vgpu->submission.workload_q_head[i]);
339 ret = intel_vgpu_init_sched_policy(vgpu);
343 vgpu->active = false;
345 return vgpu;
348 vfree(vgpu);
354 * @vgpu: virtual GPU
359 void intel_gvt_destroy_idle_vgpu(struct intel_vgpu *vgpu)
361 mutex_lock(&vgpu->vgpu_lock);
362 intel_vgpu_clean_sched_policy(vgpu);
363 mutex_unlock(&vgpu->vgpu_lock);
365 vfree(vgpu);
372 struct intel_vgpu *vgpu;
379 vgpu = vzalloc(sizeof(*vgpu));
380 if (!vgpu)
383 ret = idr_alloc(&gvt->vgpu_idr, vgpu, IDLE_VGPU_IDR + 1, GVT_MAX_VGPU,
388 vgpu->id = ret;
389 vgpu->handle = param->handle;
390 vgpu->gvt = gvt;
391 vgpu->sched_ctl.weight = param->weight;
392 mutex_init(&vgpu->vgpu_lock);
393 mutex_init(&vgpu->dmabuf_lock);
394 INIT_LIST_HEAD(&vgpu->dmabuf_obj_list_head);
395 INIT_RADIX_TREE(&vgpu->page_track_tree, GFP_KERNEL);
396 idr_init(&vgpu->object_idr);
397 intel_vgpu_init_cfg_space(vgpu, param->primary);
398 vgpu->d3_entered = false;
400 ret = intel_vgpu_init_mmio(vgpu);
404 ret = intel_vgpu_alloc_resource(vgpu, param);
408 populate_pvinfo_page(vgpu);
410 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
414 ret = intel_vgpu_init_gtt(vgpu);
418 ret = intel_vgpu_init_opregion(vgpu);
422 ret = intel_vgpu_init_display(vgpu, param->resolution);
426 ret = intel_vgpu_setup_submission(vgpu);
430 ret = intel_vgpu_init_sched_policy(vgpu);
434 intel_gvt_debugfs_add_vgpu(vgpu);
436 ret = intel_gvt_hypervisor_set_opregion(vgpu);
441 ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_B);
443 ret = intel_gvt_hypervisor_set_edid(vgpu, PORT_D);
447 return vgpu;
450 intel_vgpu_clean_sched_policy(vgpu);
452 intel_vgpu_clean_submission(vgpu);
454 intel_vgpu_clean_display(vgpu);
456 intel_vgpu_clean_opregion(vgpu);
458 intel_vgpu_clean_gtt(vgpu);
460 intel_gvt_hypervisor_detach_vgpu(vgpu);
462 intel_vgpu_free_resource(vgpu);
464 intel_vgpu_clean_mmio(vgpu);
466 idr_remove(&gvt->vgpu_idr, vgpu->id);
468 vfree(vgpu);
486 struct intel_vgpu *vgpu;
501 vgpu = __intel_gvt_create_vgpu(gvt, ¶m);
502 if (!IS_ERR(vgpu))
507 return vgpu;
512 * @vgpu: virtual GPU
517 * device model reset or GT reset. The caller should hold the vgpu lock.
538 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
541 struct intel_gvt *gvt = vgpu->gvt;
546 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
547 vgpu->id, dmlr, engine_mask);
549 vgpu->resetting_eng = resetting_eng;
551 intel_vgpu_stop_schedule(vgpu);
554 * scheduler when the reset is triggered by current vgpu.
557 mutex_unlock(&vgpu->vgpu_lock);
558 intel_gvt_wait_vgpu_idle(vgpu);
559 mutex_lock(&vgpu->vgpu_lock);
562 intel_vgpu_reset_submission(vgpu, resetting_eng);
565 intel_vgpu_select_submission_ops(vgpu, ALL_ENGINES, 0);
567 intel_vgpu_invalidate_ppgtt(vgpu);
570 if(!vgpu->d3_entered) {
571 intel_vgpu_invalidate_ppgtt(vgpu);
572 intel_vgpu_destroy_all_ppgtt_mm(vgpu);
574 intel_vgpu_reset_ggtt(vgpu, true);
575 intel_vgpu_reset_resource(vgpu);
578 intel_vgpu_reset_mmio(vgpu, dmlr);
579 populate_pvinfo_page(vgpu);
582 intel_vgpu_reset_display(vgpu);
583 intel_vgpu_reset_cfg_space(vgpu);
585 vgpu->failsafe = false;
590 if(vgpu->d3_entered)
591 vgpu->d3_entered = false;
593 vgpu->pv_notified = false;
597 vgpu->resetting_eng = 0;
598 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
604 * @vgpu: virtual GPU
609 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
611 mutex_lock(&vgpu->vgpu_lock);
612 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
613 mutex_unlock(&vgpu->vgpu_lock);