Lines Matching refs:vgpu
41 * @vgpu: a vGPU
47 int intel_vgpu_gpa_to_mmio_offset(struct intel_vgpu *vgpu, u64 gpa)
49 u64 gttmmio_gpa = intel_vgpu_get_bar_gpa(vgpu, PCI_BASE_ADDRESS_0);
60 static void failsafe_emulate_mmio_rw(struct intel_vgpu *vgpu, u64 pa,
67 if (!vgpu || !p_data)
70 gvt = vgpu->gvt;
71 mutex_lock(&vgpu->vgpu_lock);
72 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
75 intel_vgpu_default_mmio_read(vgpu, offset, p_data,
78 intel_vgpu_default_mmio_write(vgpu, offset, p_data,
82 pt = vgpu->gtt.ggtt_mm->ggtt_mm.virtual_ggtt + offset;
89 mutex_unlock(&vgpu->vgpu_lock);
94 * @vgpu: a vGPU
102 int intel_vgpu_emulate_mmio_read(struct intel_vgpu *vgpu, u64 pa,
105 struct intel_gvt *gvt = vgpu->gvt;
110 if (vgpu->failsafe) {
111 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, true);
114 mutex_lock(&vgpu->vgpu_lock);
116 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
131 ret = intel_vgpu_emulate_ggtt_mmio_read(vgpu, offset,
139 ret = intel_gvt_hypervisor_read_gpa(vgpu, pa, p_data, bytes);
151 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, true);
163 mutex_unlock(&vgpu->vgpu_lock);
169 * @vgpu: a vGPU
177 int intel_vgpu_emulate_mmio_write(struct intel_vgpu *vgpu, u64 pa,
180 struct intel_gvt *gvt = vgpu->gvt;
185 if (vgpu->failsafe) {
186 failsafe_emulate_mmio_rw(vgpu, pa, p_data, bytes, false);
190 mutex_lock(&vgpu->vgpu_lock);
192 offset = intel_vgpu_gpa_to_mmio_offset(vgpu, pa);
207 ret = intel_vgpu_emulate_ggtt_mmio_write(vgpu, offset,
215 ret = intel_gvt_hypervisor_write_gpa(vgpu, pa, p_data, bytes);
219 ret = intel_vgpu_mmio_reg_rw(vgpu, offset, p_data, bytes, false);
230 mutex_unlock(&vgpu->vgpu_lock);
237 * @vgpu: a vGPU
240 void intel_vgpu_reset_mmio(struct intel_vgpu *vgpu, bool dmlr)
242 struct intel_gvt *gvt = vgpu->gvt;
247 memcpy(vgpu->mmio.vreg, mmio, info->mmio_size);
249 vgpu_vreg_t(vgpu, GEN6_GT_THREAD_STATUS_REG) = 0;
252 vgpu_vreg_t(vgpu, GEN6_GT_CORE_STATUS) = 0;
255 vgpu_vreg_t(vgpu, GUC_STATUS) |= GS_MIA_IN_RESET;
257 if (IS_BROXTON(vgpu->gvt->gt->i915)) {
258 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &=
260 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
262 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
264 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &=
266 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &=
268 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
270 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
273 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
275 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
278 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
280 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
283 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
295 memcpy(vgpu->mmio.vreg, mmio, GVT_GEN8_MMIO_RESET_OFFSET);
302 * @vgpu: a vGPU
307 int intel_vgpu_init_mmio(struct intel_vgpu *vgpu)
309 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
311 vgpu->mmio.vreg = vzalloc(info->mmio_size);
312 if (!vgpu->mmio.vreg)
315 intel_vgpu_reset_mmio(vgpu, true);
322 * @vgpu: a vGPU
325 void intel_vgpu_clean_mmio(struct intel_vgpu *vgpu)
327 vfree(vgpu->mmio.vreg);
328 vgpu->mmio.vreg = NULL;