Lines Matching refs:ret
158 int ret;
165 ret = vfio_group_unpin_pages(vdev->vfio_group, &cur_gfn, 1);
166 drm_WARN_ON(&i915->drm, ret != 1);
178 int ret;
189 ret = vfio_group_pin_pages(vdev->vfio_group, &cur_gfn, 1,
191 if (ret != 1) {
192 gvt_vgpu_err("vfio_pin_pages failed for gfn 0x%lx, ret %d\n",
193 cur_gfn, ret);
200 ret = -EFAULT;
208 ret = -EINVAL;
218 return ret;
226 int ret;
228 ret = gvt_pin_guest_page(vgpu, gfn, size, &page);
229 if (ret)
230 return ret;
235 gvt_vgpu_err("DMA mapping failed for pfn 0x%lx, ret %d\n",
236 page_to_pfn(page), ret);
553 int ret;
561 ret = handle_edid_regs(vgpu, region, buf, count, pos, iswrite);
564 ret = handle_edid_blob(region, buf, count, pos, iswrite);
567 if (ret < 0)
570 return ret;
628 int ret;
643 ret = intel_vgpu_register_reg(vgpu,
649 return ret;
657 int ret;
671 ret = intel_vgpu_register_reg(vgpu,
679 return ret;
698 int ret;
707 ret = -EINVAL;
713 ret = vgpu == NULL ? -EFAULT : PTR_ERR(vgpu);
714 gvt_err("failed to create intel vgpu: %d\n", ret);
725 ret = 0;
728 return ret;
797 int ret;
804 ret = vfio_register_notifier(mdev_dev(mdev), VFIO_IOMMU_NOTIFY, &events,
806 if (ret != 0) {
808 ret);
813 ret = vfio_register_notifier(mdev_dev(mdev), VFIO_GROUP_NOTIFY, &events,
815 if (ret != 0) {
817 ret);
823 ret = !vfio_group ? -EFAULT : PTR_ERR(vfio_group);
833 ret = -ENODEV;
837 ret = kvmgt_guest_init(mdev);
838 if (ret)
844 return ret;
858 return ret;
878 int ret;
888 ret = vfio_unregister_notifier(mdev_dev(vdev->mdev), VFIO_IOMMU_NOTIFY,
890 drm_WARN(&i915->drm, ret,
891 "vfio_unregister_notifier for iommu failed: %d\n", ret);
893 ret = vfio_unregister_notifier(mdev_dev(vdev->mdev), VFIO_GROUP_NOTIFY,
895 drm_WARN(&i915->drm, ret,
896 "vfio_unregister_notifier for group failed: %d\n", ret);
957 int ret;
960 ret = intel_gvt_ops->emulate_mmio_write(vgpu,
963 ret = intel_gvt_ops->emulate_mmio_read(vgpu,
965 return ret;
1008 int ret = -EINVAL;
1019 ret = intel_gvt_ops->emulate_cfg_write(vgpu, pos,
1022 ret = intel_gvt_ops->emulate_cfg_read(vgpu, pos,
1026 ret = intel_vgpu_bar_rw(vgpu, PCI_BASE_ADDRESS_0, pos,
1030 ret = intel_vgpu_aperture_rw(vgpu, pos, buf, count, is_write);
1048 return ret == 0 ? count : ret;
1074 int ret;
1084 ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
1086 if (ret <= 0)
1096 ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
1098 if (ret <= 0)
1108 ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
1110 if (ret <= 0)
1120 ret = intel_vgpu_rw(mdev, &val, sizeof(val), ppos,
1122 if (ret <= 0)
1148 int ret;
1161 ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
1163 if (ret <= 0)
1173 ret = intel_vgpu_rw(mdev, (char *)&val, sizeof(val),
1175 if (ret <= 0)
1185 ret = intel_vgpu_rw(mdev, (char *)&val,
1187 if (ret <= 0)
1197 ret = intel_vgpu_rw(mdev, &val, sizeof(val),
1199 if (ret <= 0)
1378 int ret;
1476 ret = vfio_info_add_capability(&caps,
1479 if (ret)
1480 return ret;
1487 ret = vfio_info_add_capability(&caps,
1491 if (ret) {
1493 return ret;
1559 int ret = 0;
1570 ret = vfio_set_irqs_validate_and_prepare(&hdr, max,
1572 if (ret) {
1584 ret = intel_vgpu_set_irqs(vgpu, hdr.flags, hdr.index,
1588 return ret;
1594 int ret = 0;
1603 ret = intel_gvt_ops->vgpu_query_plane(vgpu, &dmabuf);
1604 if (ret != 0)
1605 return ret;
1792 bool ret = false;
1801 ret = true;
1807 return ret;
1955 int ret;
1967 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size);
1968 if (ret)
1971 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size);
1972 if (ret)
1979 ret = gvt_dma_map_page(vgpu, gfn, dma_addr, size);
1980 if (ret)
1983 ret = __gvt_cache_add(vgpu, gfn, *dma_addr, size);
1984 if (ret)
1998 return ret;
2006 int ret = 0;
2019 ret = -ENOMEM;
2022 return ret;
2089 bool ret;
2098 ret = kvm_is_visible_gfn(kvm, gfn);
2101 return ret;