Lines Matching refs:irq
45 #define get_event_virt_handler(irq, e) (irq->events[e].v_handler)
46 #define get_irq_info(irq, e) (irq->events[e].info)
48 #define irq_to_gvt(irq) \
49 container_of(irq, struct intel_gvt, irq)
150 struct intel_gvt_irq *irq = &gvt->irq;
153 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
154 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg)
155 return irq->info[i];
179 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
209 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
217 * GEN8_MASTER_IRQ is a special irq register,
249 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
325 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
326 struct intel_gvt_irq_map *map = irq->irq_map;
339 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
344 up_irq_info = irq->info[map->up_irq_group];
347 irq->info[map->up_irq_group]);
378 static void init_irq_map(struct intel_gvt_irq *irq)
384 for (map = irq->irq_map; map->up_irq_bit != -1; map++) {
385 up_info = irq->info[map->up_irq_group];
387 down_info = irq->info[map->down_irq_group];
404 static void propagate_event(struct intel_gvt_irq *irq,
411 info = get_irq_info(irq, event);
416 bit = irq->events[event].bit;
427 static void handle_default_event_virt(struct intel_gvt_irq *irq,
430 if (!vgpu->irq.irq_warn_once[event]) {
433 vgpu->irq.irq_warn_once[event] = true;
435 propagate_event(irq, event, vgpu);
470 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
477 for_each_set_bit(i, irq->irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX) {
478 struct intel_gvt_irq_info *info = irq->info[i];
496 struct intel_gvt_irq *irq)
498 struct intel_gvt *gvt = irq_to_gvt(irq);
514 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_MASTER, &gen8_master_info);
515 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT0, &gen8_gt0_info);
516 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT1, &gen8_gt1_info);
517 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT2, &gen8_gt2_info);
518 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_GT3, &gen8_gt3_info);
519 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_A, &gen8_de_pipe_a_info);
520 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_B, &gen8_de_pipe_b_info);
521 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PIPE_C, &gen8_de_pipe_c_info);
522 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_PORT, &gen8_de_port_info);
523 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_DE_MISC, &gen8_de_misc_info);
524 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCU, &gen8_pcu_info);
525 SET_IRQ_GROUP(irq, INTEL_GVT_IRQ_INFO_PCH, &gvt_base_pch_info);
530 SET_BIT_INFO(irq, 0, RCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
531 SET_BIT_INFO(irq, 4, RCS_PIPE_CONTROL, INTEL_GVT_IRQ_INFO_GT0);
532 SET_BIT_INFO(irq, 8, RCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
534 SET_BIT_INFO(irq, 16, BCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT0);
535 SET_BIT_INFO(irq, 20, BCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT0);
536 SET_BIT_INFO(irq, 24, BCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT0);
539 SET_BIT_INFO(irq, 0, VCS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT1);
540 SET_BIT_INFO(irq, 4, VCS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT1);
541 SET_BIT_INFO(irq, 8, VCS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT1);
544 SET_BIT_INFO(irq, 16, VCS2_MI_USER_INTERRUPT,
546 SET_BIT_INFO(irq, 20, VCS2_MI_FLUSH_DW,
548 SET_BIT_INFO(irq, 24, VCS2_AS_CONTEXT_SWITCH,
553 SET_BIT_INFO(irq, 0, VECS_MI_USER_INTERRUPT, INTEL_GVT_IRQ_INFO_GT3);
554 SET_BIT_INFO(irq, 4, VECS_MI_FLUSH_DW, INTEL_GVT_IRQ_INFO_GT3);
555 SET_BIT_INFO(irq, 8, VECS_AS_CONTEXT_SWITCH, INTEL_GVT_IRQ_INFO_GT3);
557 SET_BIT_INFO(irq, 0, PIPE_A_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
558 SET_BIT_INFO(irq, 0, PIPE_B_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
559 SET_BIT_INFO(irq, 0, PIPE_C_VBLANK, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
562 SET_BIT_INFO(irq, 0, AUX_CHANNEL_A, INTEL_GVT_IRQ_INFO_DE_PORT);
563 SET_BIT_INFO(irq, 3, DP_A_HOTPLUG, INTEL_GVT_IRQ_INFO_DE_PORT);
566 SET_BIT_INFO(irq, 0, GSE, INTEL_GVT_IRQ_INFO_DE_MISC);
569 SET_BIT_INFO(irq, 17, GMBUS, INTEL_GVT_IRQ_INFO_PCH);
570 SET_BIT_INFO(irq, 19, CRT_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
571 SET_BIT_INFO(irq, 21, DP_B_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
572 SET_BIT_INFO(irq, 22, DP_C_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
573 SET_BIT_INFO(irq, 23, DP_D_HOTPLUG, INTEL_GVT_IRQ_INFO_PCH);
576 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_PCH);
577 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_PCH);
578 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_PCH);
580 SET_BIT_INFO(irq, 4, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
581 SET_BIT_INFO(irq, 5, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
583 SET_BIT_INFO(irq, 4, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
584 SET_BIT_INFO(irq, 5, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
586 SET_BIT_INFO(irq, 4, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
587 SET_BIT_INFO(irq, 5, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
589 SET_BIT_INFO(irq, 25, AUX_CHANNEL_B, INTEL_GVT_IRQ_INFO_DE_PORT);
590 SET_BIT_INFO(irq, 26, AUX_CHANNEL_C, INTEL_GVT_IRQ_INFO_DE_PORT);
591 SET_BIT_INFO(irq, 27, AUX_CHANNEL_D, INTEL_GVT_IRQ_INFO_DE_PORT);
593 SET_BIT_INFO(irq, 3, PRIMARY_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
594 SET_BIT_INFO(irq, 3, PRIMARY_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
595 SET_BIT_INFO(irq, 3, PRIMARY_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
597 SET_BIT_INFO(irq, 4, SPRITE_A_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_A);
598 SET_BIT_INFO(irq, 4, SPRITE_B_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_B);
599 SET_BIT_INFO(irq, 4, SPRITE_C_FLIP_DONE, INTEL_GVT_IRQ_INFO_DE_PIPE_C);
603 SET_BIT_INFO(irq, 24, PCU_THERMAL, INTEL_GVT_IRQ_INFO_PCU);
604 SET_BIT_INFO(irq, 25, PCU_PCODE2DRIVER_MAILBOX, INTEL_GVT_IRQ_INFO_PCU);
627 struct intel_gvt_irq *irq = &gvt->irq;
629 struct intel_gvt_irq_ops *ops = gvt->irq.ops;
631 handler = get_event_virt_handler(irq, event);
634 handler(irq, event, vgpu);
640 struct intel_gvt_irq *irq)
645 irq->events[i].info = NULL;
646 irq->events[i].v_handler = handle_default_event_virt;
653 struct intel_gvt_irq *irq;
657 irq = container_of(vblank_timer, struct intel_gvt_irq, vblank_timer);
658 gvt = container_of(irq, struct intel_gvt, irq);
675 struct intel_gvt_irq *irq = &gvt->irq;
677 hrtimer_cancel(&irq->vblank_timer.timer);
694 struct intel_gvt_irq *irq = &gvt->irq;
695 struct intel_gvt_vblank_timer *vblank_timer = &irq->vblank_timer;
697 gvt_dbg_core("init irq framework\n");
699 irq->ops = &gen8_irq_ops;
700 irq->irq_map = gen8_irq_map;
703 init_events(irq);
706 irq->ops->init_irq(irq);
708 init_irq_map(irq);