Lines Matching defs:vgpu
51 static void update_upstream_irq(struct intel_vgpu *vgpu,
163 * @vgpu: a vGPU
175 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
178 struct intel_gvt *gvt = vgpu->gvt;
182 trace_write_ir(vgpu->id, "IMR", reg, imr, vgpu_vreg(vgpu, reg),
183 (vgpu_vreg(vgpu, reg) ^ imr));
185 vgpu_vreg(vgpu, reg) = imr;
187 ops->check_pending_irq(vgpu);
194 * @vgpu: a vGPU
205 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
208 struct intel_gvt *gvt = vgpu->gvt;
211 u32 virtual_ier = vgpu_vreg(vgpu, reg);
213 trace_write_ir(vgpu->id, "MASTER_IRQ", reg, ier, virtual_ier,
223 vgpu_vreg(vgpu, reg) &= ~GEN8_MASTER_IRQ_CONTROL;
224 vgpu_vreg(vgpu, reg) |= ier;
226 ops->check_pending_irq(vgpu);
233 * @vgpu: a vGPU
244 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
247 struct intel_gvt *gvt = vgpu->gvt;
253 trace_write_ir(vgpu->id, "IER", reg, ier, vgpu_vreg(vgpu, reg),
254 (vgpu_vreg(vgpu, reg) ^ ier));
256 vgpu_vreg(vgpu, reg) = ier;
263 update_upstream_irq(vgpu, info);
265 ops->check_pending_irq(vgpu);
272 * @vgpu: a vGPU
283 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
286 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
287 struct intel_gvt_irq_info *info = regbase_to_irq_info(vgpu->gvt,
291 trace_write_ir(vgpu->id, "IIR", reg, iir, vgpu_vreg(vgpu, reg),
292 (vgpu_vreg(vgpu, reg) ^ iir));
297 vgpu_vreg(vgpu, reg) &= ~iir;
300 update_upstream_irq(vgpu, info);
321 static void update_upstream_irq(struct intel_vgpu *vgpu,
324 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
325 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
331 u32 val = vgpu_vreg(vgpu,
333 & vgpu_vreg(vgpu,
363 vgpu_vreg(vgpu, isr) &= ~clear_bits;
364 vgpu_vreg(vgpu, isr) |= set_bits;
371 vgpu_vreg(vgpu, iir) |= (set_bits & ~vgpu_vreg(vgpu, imr));
375 update_upstream_irq(vgpu, up_irq_info);
399 static int inject_virtual_interrupt(struct intel_vgpu *vgpu)
401 return intel_gvt_hypervisor_inject_msi(vgpu);
405 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
418 if (!test_bit(bit, (void *)&vgpu_vreg(vgpu,
420 trace_propagate_event(vgpu->id, irq_name[event], bit);
421 set_bit(bit, (void *)&vgpu_vreg(vgpu,
428 enum intel_gvt_event_type event, struct intel_vgpu *vgpu)
430 if (!vgpu->irq.irq_warn_once[event]) {
431 gvt_dbg_core("vgpu%d: IRQ receive event %d (%s)\n",
432 vgpu->id, event, irq_name[event]);
433 vgpu->irq.irq_warn_once[event] = true;
435 propagate_event(irq, event, vgpu);
468 static void gen8_check_pending_irq(struct intel_vgpu *vgpu)
470 struct intel_gvt_irq *irq = &vgpu->gvt->irq;
473 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) &
485 if ((vgpu_vreg(vgpu, regbase_to_iir(reg_base))
486 & vgpu_vreg(vgpu, regbase_to_ier(reg_base))))
487 update_upstream_irq(vgpu, info);
490 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ))
492 inject_virtual_interrupt(vgpu);
614 * @vgpu: a vGPU
622 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
625 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
626 struct intel_gvt *gvt = vgpu->gvt;
634 handler(irq, event, vgpu);
636 ops->check_pending_irq(vgpu);