Lines Matching refs:pipe
585 enum pipe pipe, unsigned int train_pattern)
592 fdi_rx_imr = FDI_RX_IMR(pipe);
593 fdi_tx_ctl = FDI_TX_CTL(pipe);
594 fdi_rx_ctl = FDI_RX_CTL(pipe);
761 u32 pipe = DSPSURF_TO_PIPE(offset);
762 int event = SKL_FLIP_EVENT(pipe, PLANE_PRIMARY);
765 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
767 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
769 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP)
772 set_bit(event, vgpu->irq.flip_done_event[pipe]);
783 u32 pipe = SPRSURF_TO_PIPE(offset);
784 int event = SKL_FLIP_EVENT(pipe, PLANE_SPRITE0);
787 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
789 if (vgpu_vreg_t(vgpu, SPRCTL(pipe)) & PLANE_CTL_ASYNC_FLIP)
792 set_bit(event, vgpu->irq.flip_done_event[pipe]);
802 enum pipe pipe = REG_50080_TO_PIPE(offset);
804 int event = SKL_FLIP_EVENT(pipe, plane);
808 vgpu_vreg_t(vgpu, DSPSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
809 vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
811 vgpu_vreg_t(vgpu, SPRSURFLIVE(pipe)) = vgpu_vreg(vgpu, offset);
817 set_bit(event, vgpu->irq.flip_done_event[pipe]);