Lines Matching defs:data
317 u32 data;
320 data = vgpu_vreg(vgpu, offset);
322 if (data & GEN6_GRDOM_FULL) {
326 if (data & GEN6_GRDOM_RENDER) {
330 if (data & GEN6_GRDOM_MEDIA) {
334 if (data & GEN6_GRDOM_BLT) {
338 if (data & GEN6_GRDOM_VECS) {
342 if (data & GEN8_GRDOM_MEDIA2) {
346 if (data & GEN9_GRDOM_GUC) {
449 u32 data;
452 data = vgpu_vreg(vgpu, offset);
454 if (data & PIPECONF_ENABLE)
698 u32 data;
703 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
704 if (data == 0x2) {
729 u32 data;
732 data = vgpu_vreg(vgpu, offset);
734 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
742 u32 data;
745 data = vgpu_vreg(vgpu, offset);
747 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
877 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
879 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
884 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
885 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
887 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
888 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
890 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
896 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
918 u32 data;
926 data = vgpu_vreg(vgpu, offset);
934 /* write to the data registers */
938 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
969 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
975 * 4 bytes, followed by (len + 1) bytes of data. See details at
983 /* unpack data from vreg to buf */
998 dpcd->data[p] = buf[t];
1008 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
1021 * reply with an AUX ACK and read data set equal to
1032 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1038 /* clear the data registers */
1043 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
1056 t = dpcd->data[addr + i - 1];
1067 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
1075 if (data & DP_AUX_CH_CTL_INTERRUPT)
1159 u32 data;
1162 data = vgpu_vreg(vgpu, offset);
1164 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1165 data |= SBI_READY;
1167 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1168 data |= SBI_RESPONSE_SUCCESS;
1170 vgpu_vreg(vgpu, offset) = data;
1265 u32 data = *(u32 *)p_data;
1270 send_display_ready_uevent(vgpu, data ? 1 : 0);
1273 handle_g2v_notification(vgpu, data);
1295 gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
1296 offset, bytes, data);
1575 u32 data = v & COMMON_RESET_DIS ? BXT_PHY_LANE_ENABLED : 0;
1579 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_A) = data;
1582 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_B) = data;
1583 vgpu_vreg(vgpu, _BXT_PHY_CTL_DDI_C) = data;
1725 u32 data = *(u32 *)p_data;
1748 execlist->elsp_dwords.data[3 - execlist->elsp_dwords.index] = data;
1764 u32 data = *(u32 *)p_data;
1776 if (IS_MASKED_BITS_ENABLED(data, 1)) {
1783 IS_MASKED_BITS_ENABLED(data, 2)) {
1792 if ((IS_MASKED_BITS_ENABLED(data, GFX_PPGTT_ENABLE) ||
1793 IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE)) &&
1798 if (IS_MASKED_BITS_ENABLED(data, GFX_RUN_LIST_ENABLE) ||
1799 IS_MASKED_BITS_DISABLED(data, GFX_RUN_LIST_ENABLE)) {
1800 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1855 u32 data;
1858 data = vgpu_vreg(vgpu, offset);
1860 if (IS_MASKED_BITS_ENABLED(data, RESET_CTL_REQUEST_RESET))
1861 data |= RESET_CTL_READY_TO_RESET;
1862 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1863 data &= ~RESET_CTL_READY_TO_RESET;
1865 vgpu_vreg(vgpu, offset) = data;
1873 u32 data = *(u32 *)p_data;
1878 if (IS_MASKED_BITS_ENABLED(data, 0x10) ||
1879 IS_MASKED_BITS_ENABLED(data, 0x8))
3496 * @data: private data given to handler
3502 int (*handler)(struct intel_gvt *gvt, u32 offset, void *data),
3503 void *data)
3510 ret = handler(gvt, e->offset, data);
3516 /* pvinfo data doesn't come from hw mmio */
3523 data);
3535 * @p_data: data return buffer
3536 * @bytes: access data length
3552 * @p_data: write data buffer
3553 * @bytes: access data length
3569 * @p_data: write data buffer
3570 * @bytes: access data length
3610 * @pdata: data buffer
3611 * @bytes: data length
3655 u64 data = 0;
3668 memcpy(&data, pdata, bytes);
3669 data &= ~ro_mask;
3670 data |= vgpu_vreg(vgpu, offset) & ro_mask;
3671 ret = mmio_info->write(vgpu, offset, &data, bytes);
3705 u32 offset, void *data)
3707 struct intel_vgpu *vgpu = data;