Lines Matching refs:gvt
37 #include "gvt.h"
74 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
92 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
94 if (drm_WARN(&i915->drm, !gvt_gmadr_is_valid(vgpu->gvt, h_addr),
98 if (gvt_gmadr_is_aperture(vgpu->gvt, h_addr))
100 + (h_addr - gvt_aperture_gmadr_base(vgpu->gvt));
103 + (h_addr - gvt_hidden_gmadr_base(vgpu->gvt));
308 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
321 e->val64 = read_pte64(vgpu->gvt->gt->ggtt, index);
333 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
346 write_pte64(vgpu->gvt->gt->ggtt, index, e->val64);
556 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
583 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
605 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
617 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
628 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
638 struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
663 struct intel_gvt *gvt = spt->vgpu->gvt;
664 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
692 struct intel_gvt *gvt = spt->vgpu->gvt;
693 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
749 struct device *kdev = &spt->vgpu->gvt->gt->i915->drm.pdev->dev;
828 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt);
834 struct device *kdev = &vgpu->gvt->gt->i915->drm.pdev->dev;
842 if (reclaim_one_ppgtt_mm(vgpu->gvt))
912 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
921 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
927 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
955 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
956 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
993 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1062 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
1081 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1145 struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1168 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1171 if (!HAS_PAGE_SIZES(vgpu->gvt->gt->i915, I915_GTT_PAGE_SIZE_2M))
1185 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1241 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1272 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1325 struct intel_gvt *gvt = vgpu->gvt;
1326 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1348 ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1369 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1448 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1449 struct intel_gvt *gvt = vgpu->gvt;
1450 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1491 struct intel_gvt *gvt = vgpu->gvt;
1502 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1510 struct intel_gvt *gvt = spt->vgpu->gvt;
1522 list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1547 struct intel_gvt *gvt = spt->vgpu->gvt;
1548 struct intel_gvt_gtt *gtt = &gvt->gtt;
1621 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1738 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1739 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
1801 struct intel_gvt *gvt = vgpu->gvt;
1802 struct intel_gvt_gtt *gtt = &gvt->gtt;
1831 struct intel_gvt *gvt = vgpu->gvt;
1832 struct intel_gvt_gtt *gtt = &gvt->gtt;
1905 struct intel_gvt *gvt = vgpu->gvt;
1938 mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1939 list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1940 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
1956 nr_entries = gvt_ggtt_gm_sz(vgpu->gvt) >> I915_GTT_PAGE_SHIFT;
1959 vgpu->gvt->device_info.gtt_entry_size));
2000 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2002 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2047 mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2049 &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
2050 mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2056 static int reclaim_one_ppgtt_mm(struct intel_gvt *gvt)
2061 mutex_lock(&gvt->gtt.ppgtt_mm_lock);
2063 list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
2070 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2074 mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2085 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2113 struct intel_gvt *gvt = vgpu->gvt;
2114 struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2115 struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2188 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2225 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2239 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2243 if (pfn != vgpu->gvt->gtt.scratch_mfn)
2251 struct intel_gvt *gvt = vgpu->gvt;
2252 const struct intel_gvt_device_info *info = &gvt->device_info;
2254 struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2332 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2344 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2348 ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2359 ggtt_invalidate(gvt->gt);
2378 const struct intel_gvt_device_info *info = &vgpu->gvt->device_info;
2394 for_each_engine(engine, vgpu->gvt->gt, i) {
2407 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
2409 struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2411 vgpu->gvt->device_info.gtt_entry_size_shift;
2414 struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev;
2472 struct device *dev = &vgpu->gvt->gt->i915->drm.pdev->dev;
2590 static void clean_spt_oos(struct intel_gvt *gvt)
2592 struct intel_gvt_gtt *gtt = &gvt->gtt;
2607 static int setup_spt_oos(struct intel_gvt *gvt)
2609 struct intel_gvt_gtt *gtt = &gvt->gtt;
2640 clean_spt_oos(gvt);
2732 * @gvt: GVT device
2740 int intel_gvt_init_gtt(struct intel_gvt *gvt)
2744 struct device *dev = &gvt->gt->i915->drm.pdev->dev;
2749 gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2750 gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2766 gvt->gtt.scratch_page = virt_to_page(page);
2767 gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2770 ret = setup_spt_oos(gvt);
2774 __free_page(gvt->gtt.scratch_page);
2778 INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2779 mutex_init(&gvt->gtt.ppgtt_mm_lock);
2785 * @gvt: GVT device
2791 void intel_gvt_clean_gtt(struct intel_gvt *gvt)
2793 struct device *dev = &gvt->gt->i915->drm.pdev->dev;
2794 dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2799 __free_page(gvt->gtt.scratch_page);
2802 clean_spt_oos(gvt);
2820 mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2822 mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2840 struct intel_gvt *gvt = vgpu->gvt;
2841 struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2847 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2870 ggtt_invalidate(gvt->gt);
2875 * @gvt: intel gvt device
2881 void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
2890 idr_for_each_entry(&(gvt)->vgpu_idr, vgpu, id) {
2898 write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
2906 write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);