Lines Matching refs:entry
161 * - type of entry inside this level page table
162 * - type of entry with PSE set
165 * e.g. give a l4 root entry type, then request to get its PSE type,
167 * table type, as we know l4 root entry doesn't have a PSE bit,
361 #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
442 * it also works, so we need to treat root pointer entry
528 /* Update entry type per pse and ips bit. */
530 struct intel_gvt_gtt_entry *entry, bool ips)
532 switch (entry->type) {
535 if (pte_ops->test_pse(entry))
536 entry->type = get_pse_type(entry->type);
540 entry->type = get_pse_type(entry->type);
543 GEM_BUG_ON(!gtt_type_is_entry(entry->type));
546 GEM_BUG_ON(entry->type == GTT_TYPE_INVALID);
553 struct intel_gvt_gtt_entry *entry, unsigned long index,
560 entry->type = mm->ppgtt_mm.root_entry_type;
563 entry, index, false, 0, mm->vgpu);
564 update_entry_type_for_real(pte_ops, entry, false);
568 struct intel_gvt_gtt_entry *entry, unsigned long index)
570 _ppgtt_get_root_entry(mm, entry, index, true);
574 struct intel_gvt_gtt_entry *entry, unsigned long index)
576 _ppgtt_get_root_entry(mm, entry, index, false);
580 struct intel_gvt_gtt_entry *entry, unsigned long index,
587 entry, index, false, 0, mm->vgpu);
591 struct intel_gvt_gtt_entry *entry, unsigned long index)
593 _ppgtt_set_root_entry(mm, entry, index, true);
597 struct intel_gvt_gtt_entry *entry, unsigned long index)
599 _ppgtt_set_root_entry(mm, entry, index, false);
603 struct intel_gvt_gtt_entry *entry, unsigned long index)
609 entry->type = GTT_TYPE_GGTT_PTE;
610 pte_ops->get_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
615 struct intel_gvt_gtt_entry *entry, unsigned long index)
621 pte_ops->set_entry(mm->ggtt_mm.virtual_ggtt, entry, index,
626 struct intel_gvt_gtt_entry *entry, unsigned long index)
632 pte_ops->get_entry(NULL, entry, index, false, 0, mm->vgpu);
636 struct intel_gvt_gtt_entry *entry, unsigned long index)
645 mm->ggtt_mm.host_ggtt_aperture[offset] = entry->val64;
648 mm->ggtt_mm.host_ggtt_hidden[offset] = entry->val64;
651 pte_ops->set_entry(NULL, entry, index, false, 0, mm->vgpu);
669 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
681 gvt_vdbg_mm("read ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
695 if (WARN(!gtt_type_is_entry(e->type), "invalid entry type\n"))
698 gvt_vdbg_mm("set ppgtt entry, spt type %d, entry type %d, index %lu, value %llx\n",
990 struct intel_gvt_gtt_entry *entry)
997 pfn = ops->get_pfn(entry);
1023 gvt_vdbg_mm("invalidate 4K entry\n");
1027 /* We don't setup 64K shadow entry so far. */
1028 WARN(1, "suspicious 64K gtt entry\n");
1031 gvt_vdbg_mm("invalidate 2M entry\n");
1039 gvt_vdbg_mm("invalidate PMUL4/PDP/PDE entry\n");
1055 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
1137 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1160 * @entry: target pfn's gtt entry
1166 struct intel_gvt_gtt_entry *entry)
1174 pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, ops->get_pfn(entry));
1193 gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1227 gvt_vdbg_mm("invalidate 4K entry\n");
1242 struct intel_gvt_gtt_entry entry = *se;
1247 gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1253 entry.type = GTT_TYPE_PPGTT_PTE_4K_ENTRY;
1254 ops->set_64k_splited(&entry);
1262 ops->set_pfn(&entry, dma_addr >> PAGE_SHIFT);
1263 ppgtt_set_shadow_entry(spt, &entry, index + i);
1285 gvt_vdbg_mm("shadow 4K gtt entry\n");
1288 gvt_vdbg_mm("shadow 64K gtt entry\n");
1296 gvt_vdbg_mm("shadow 2M gtt entry\n");
1305 gvt_vgpu_err("GVT doesn't support 1GB entry\n");
1360 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1375 gvt_vdbg_mm("destroy old shadow entry, type %d, index %lu, value %llx\n",
1397 /* We don't setup 64K shadow entry so far. */
1399 "suspicious 64K entry\n");
1405 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1421 gvt_vdbg_mm("add shadow entry: type %d, index %lu, value %llx\n",
1440 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1629 * Adding the new entry first and then removing the old one, that can
1671 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1749 * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1755 gvt_vdbg_mm("Ignore write to unused PTE entry, index %lu\n",
1894 * @root_entry_type: ppgtt root entry type
2159 /* walk the shadow page table and get gpa from guest entry */
2237 struct intel_gvt_gtt_entry *entry)
2242 pfn = pte_ops->get_pfn(entry);
2277 /* If ggtt entry size is 8 bytes, and it's split into two 4 bytes
2339 gvt_vgpu_err("fail to populate guest ggtt entry\n");
2340 /* guest driver may read/write the entry when partial
2341 * update the entry in this situation p2m will fail
2342 * settting the shadow entry to point to a scratch page
2455 /* The entry parameters like present/writeable/cache type
2683 * @root_entry_type: ppgtt root entry type
2830 * intel_vgpu_reset_ggtt - reset the GGTT entry
2842 struct intel_gvt_gtt_entry entry = {.type = GTT_TYPE_GGTT_PTE};
2847 pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2848 pte_ops->set_present(&entry);
2857 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2867 ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);