Lines Matching defs:gtt

361 #define GTT_SPTE_FLAG_64K_SPLITED BIT(52) /* splited 64K gtt entry */
556 	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
583 	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
605 	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
617 	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
628 	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
638 	struct intel_gvt_gtt_pte_ops *pte_ops = mm->vgpu->gvt->gtt.pte_ops;
664 	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
693 	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
756 	radix_tree_delete(&spt->vgpu->gtt.spt_tree, spt->shadow_page.mfn);
777 	radix_tree_for_each_slot(slot, &vgpu->gtt.spt_tree, &iter, 0) {
825 	return radix_tree_lookup(&vgpu->gtt.spt_tree, mfn);
867 	ret = radix_tree_insert(&vgpu->gtt.spt_tree, spt->shadow_page.mfn, spt);
921 		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
927 		    spt->vgpu->gvt->gtt.pte_ops->test_present(e))
956 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
977 			vgpu->gtt.scratch_pt[cur_pt_type].page_mfn)
993 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1001 	if (!pfn || pfn == vgpu->gtt.scratch_pt[type].page_mfn)
1028 			WARN(1, "suspicious 64K gtt entry\n");
1081 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1145 	struct intel_gvt_gtt_pte_ops *ops = s->vgpu->gvt->gtt.pte_ops;
1160  * @entry: target pfn's gtt entry
1162  * Return 1 if 2MB huge gtt shadowing is possilbe, 0 if miscondition,
1168 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1185 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1193 	gvt_dbg_mm("Split 2M gtt entry, index %lu\n", index);
1241 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1247 	gvt_vdbg_mm("Split 64K gtt entry, index %lu\n", index);
1272 	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
1285 		gvt_vdbg_mm("shadow 4K gtt entry\n");
1288 		gvt_vdbg_mm("shadow 64K gtt entry\n");
1296 		gvt_vdbg_mm("shadow 2M gtt entry\n");
1326 	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1348 				ops->set_pfn(&se, gvt->gtt.scratch_mfn);
1369 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1382 	    vgpu->gtt.scratch_pt[spt->shadow_page.type].page_mfn)
1450 	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
1502 	list_move_tail(&oos_page->list, &gvt->gtt.oos_page_free_list_head);
1522 	list_move_tail(&oos_page->list, &gvt->gtt.oos_page_use_list_head);
1548 	struct intel_gvt_gtt *gtt = &gvt->gtt;
1554 	if (list_empty(&gtt->oos_page_free_list_head)) {
1555 		oos_page = container_of(gtt->oos_page_use_list_head.next,
1564 		oos_page = container_of(gtt->oos_page_free_list_head.next,
1579 	list_add_tail(&oos_page->vm_list, &spt->vgpu->gtt.oos_page_list_head);
1602 	list_for_each_safe(pos, n, &vgpu->gtt.oos_page_list_head) {
1621 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1653 					vgpu->gtt.scratch_pt[type].page_mfn);
1660 				     vgpu->gtt.scratch_pt[type].page_mfn);
1664 				     vgpu->gtt.scratch_pt[type].page_mfn);
1693 			&spt->vgpu->gtt.post_shadow_list_head);
1714 	list_for_each_safe(pos, n, &vgpu->gtt.post_shadow_list_head) {
1738 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
1749 	 * For page table which has 64K gtt entry, only PTE#0, PTE#16,
1772 			ops->set_pfn(&se, vgpu->gtt.scratch_pt[type].page_mfn);
1802 	struct intel_gvt_gtt *gtt = &gvt->gtt;
1803 	struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1832 	struct intel_gvt_gtt *gtt = &gvt->gtt;
1833 	struct intel_gvt_gtt_pte_ops *ops = gtt->pte_ops;
1936 	list_add_tail(&mm->ppgtt_mm.list, &vgpu->gtt.ppgtt_mm_list_head);
1938 	mutex_lock(&gvt->gtt.ppgtt_mm_lock);
1939 	list_add_tail(&mm->ppgtt_mm.lru_list, &gvt->gtt.ppgtt_mm_lru_list_head);
1940 	mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2000 		mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2002 		mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2047 		mutex_lock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2049 			       &mm->vgpu->gvt->gtt.ppgtt_mm_lru_list_head);
2050 		mutex_unlock(&mm->vgpu->gvt->gtt.ppgtt_mm_lock);
2061 	mutex_lock(&gvt->gtt.ppgtt_mm_lock);
2063 	list_for_each_safe(pos, n, &gvt->gtt.ppgtt_mm_lru_list_head) {
2070 		mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2074 	mutex_unlock(&gvt->gtt.ppgtt_mm_lock);
2085 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2114 	struct intel_gvt_gtt_pte_ops *pte_ops = gvt->gtt.pte_ops;
2115 	struct intel_gvt_gtt_gma_ops *gma_ops = gvt->gtt.gma_ops;
2187 	struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2239 	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2243 	if (pfn != vgpu->gvt->gtt.scratch_mfn)
2253 	struct intel_vgpu_mm *ggtt_mm = vgpu->gtt.ggtt_mm;
2254 	struct intel_gvt_gtt_pte_ops *ops = gvt->gtt.pte_ops;
2332 			ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2344 			ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2348 		ops->set_pfn(&m, gvt->gtt.scratch_mfn);
2408 	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2409 	struct intel_gvt_gtt_pte_ops *ops = vgpu->gvt->gtt.pte_ops;
2434 	gtt->scratch_pt[type].page_mfn =
2436 	gtt->scratch_pt[type].page = virt_to_page(scratch_pt);
2438 			vgpu->id, type, gtt->scratch_pt[type].page_mfn);
2453 		ops->set_pfn(&se, gtt->scratch_pt[type - 1].page_mfn);
2476 		if (vgpu->gtt.scratch_pt[i].page != NULL) {
2477 			daddr = (dma_addr_t)(vgpu->gtt.scratch_pt[i].page_mfn <<
2480 			__free_page(vgpu->gtt.scratch_pt[i].page);
2481 			vgpu->gtt.scratch_pt[i].page = NULL;
2482 			vgpu->gtt.scratch_pt[i].page_mfn = 0;
2518 	struct intel_vgpu_gtt *gtt = &vgpu->gtt;
2520 	INIT_RADIX_TREE(&gtt->spt_tree, GFP_KERNEL);
2522 	INIT_LIST_HEAD(&gtt->ppgtt_mm_list_head);
2523 	INIT_LIST_HEAD(&gtt->oos_page_list_head);
2524 	INIT_LIST_HEAD(&gtt->post_shadow_list_head);
2526 	gtt->ggtt_mm = intel_vgpu_create_ggtt_mm(vgpu);
2527 	if (IS_ERR(gtt->ggtt_mm)) {
2529 		return PTR_ERR(gtt->ggtt_mm);
2534 	INIT_LIST_HEAD(&gtt->ggtt_mm->ggtt_mm.partial_pte_list);
2544 	list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2549 	if (GEM_WARN_ON(!list_empty(&vgpu->gtt.ppgtt_mm_list_head)))
2552 	if (GEM_WARN_ON(!radix_tree_empty(&vgpu->gtt.spt_tree))) {
2563 				 &vgpu->gtt.ggtt_mm->ggtt_mm.partial_pte_list,
2569 	intel_vgpu_destroy_mm(vgpu->gtt.ggtt_mm);
2570 	vgpu->gtt.ggtt_mm = NULL;
2592 	struct intel_gvt_gtt *gtt = &gvt->gtt;
2596 	WARN(!list_empty(&gtt->oos_page_use_list_head),
2599 	list_for_each_safe(pos, n, &gtt->oos_page_free_list_head) {
2609 	struct intel_gvt_gtt *gtt = &gvt->gtt;
2614 	INIT_LIST_HEAD(&gtt->oos_page_free_list_head);
2615 	INIT_LIST_HEAD(&gtt->oos_page_use_list_head);
2633 		list_add_tail(&oos_page->list, &gtt->oos_page_free_list_head);
2660 	list_for_each(pos, &vgpu->gtt.ppgtt_mm_list_head) {
2747 	gvt_dbg_core("init gtt\n");
2749 	gvt->gtt.pte_ops = &gen8_gtt_pte_ops;
2750 	gvt->gtt.gma_ops = &gen8_gtt_gma_ops;
2766 	gvt->gtt.scratch_page = virt_to_page(page);
2767 	gvt->gtt.scratch_mfn = (unsigned long)(daddr >> I915_GTT_PAGE_SHIFT);
2774 			__free_page(gvt->gtt.scratch_page);
2778 	INIT_LIST_HEAD(&gvt->gtt.ppgtt_mm_lru_list_head);
2779 	mutex_init(&gvt->gtt.ppgtt_mm_lock);
2794 	dma_addr_t daddr = (dma_addr_t)(gvt->gtt.scratch_mfn <<
2799 	__free_page(gvt->gtt.scratch_page);
2817 	list_for_each_safe(pos, n, &vgpu->gtt.ppgtt_mm_list_head) {
2820 			mutex_lock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2822 			mutex_unlock(&vgpu->gvt->gtt.ppgtt_mm_lock);
2841 	struct intel_gvt_gtt_pte_ops *pte_ops = vgpu->gvt->gtt.pte_ops;
2847 	pte_ops->set_pfn(&entry, gvt->gtt.scratch_mfn);
2854 			ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2857 		ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2864 			ggtt_get_host_entry(vgpu->gtt.ggtt_mm, &old_entry, index);
2867 		ggtt_set_host_entry(vgpu->gtt.ggtt_mm, &entry, index++);
2891 		mm = vgpu->gtt.ggtt_mm;