Lines Matching defs:vgpu

49 static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
51 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;
68 	if (intel_vgpu_has_monitor_on_port(vgpu, edid->port)) {
70 			intel_vgpu_port(vgpu, edid->port)->edid;
126 static void reset_gmbus_controller(struct intel_vgpu *vgpu)
128 	vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
129 	if (!vgpu->display.i2c_edid.edid_available)
130 		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
131 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
135 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
138 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
141 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
143 	pin_select = vgpu_vreg(vgpu, offset) & _GMBUS_PIN_SEL_MASK;
145 	intel_vgpu_init_i2c_edid(vgpu);
159 	vgpu->display.i2c_edid.state = I2C_GMBUS;
160 	vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
162 	vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
163 	vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
165 	if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
166 			!intel_vgpu_port_is_dp(vgpu, port)) {
167 		vgpu->display.i2c_edid.port = port;
168 		vgpu->display.i2c_edid.edid_available = true;
169 		vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
171 		vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
175 static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
178 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
182 	if (vgpu_vreg(vgpu, offset) & GMBUS_SW_CLR_INT) {
184 			vgpu_vreg(vgpu, offset) &= ~GMBUS_SW_CLR_INT;
185 			reset_gmbus_controller(vgpu);
198 			vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
199 			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
212 		/* vgpu gmbus only support EDID */
217 				"vgpu%d: unsupported gmbus slave addr(0x%x)\n"
219 					vgpu->id, slave_addr);
237 			if (gmbus1_bus_cycle(vgpu_vreg(vgpu, offset))
239 				intel_vgpu_init_i2c_edid(vgpu);
247 				vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
259 			vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
271 		vgpu_vreg(vgpu, offset) = wvalue;
276 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
279 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
285 static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
290 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
297 	if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
299 			memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
306 			byte_data = edid_get_byte(vgpu);
310 		memcpy(&vgpu_vreg(vgpu, offset), &reg_data, byte_count);
311 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
325 			intel_vgpu_init_i2c_edid(vgpu);
332 		memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
338 static int gmbus2_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
341 	u32 value = vgpu_vreg(vgpu, offset);
343 	if (!(vgpu_vreg(vgpu, offset) & GMBUS_INUSE))
344 		vgpu_vreg(vgpu, offset) |= GMBUS_INUSE;
349 static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
355 		vgpu_vreg(vgpu, offset) &= ~GMBUS_INUSE;
362  * @vgpu: a vGPU
373 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
376 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
382 		return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
384 		return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
386 	memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
392  * @vgpu: a vGPU
403 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
406 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
412 		return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
414 		return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
416 		return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
418 		return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
420 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
469  * @vgpu: a vGPU
477 void intel_gvt_i2c_handle_aux_ch_write(struct intel_vgpu *vgpu,
482 	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
483 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
491 		vgpu_vreg(vgpu, offset) = value;
497 	msg = vgpu_vreg(vgpu, offset + 4);
508 	vgpu_vreg(vgpu, offset) =
516 			intel_vgpu_init_i2c_edid(vgpu);
523 				intel_vgpu_init_i2c_edid(vgpu);
528 				if (intel_vgpu_has_monitor_on_port(vgpu,
530 					intel_vgpu_port_is_dp(vgpu, port_idx))
547 			unsigned char val = edid_get_byte(vgpu);
558 	vgpu_vreg(vgpu, offset + 4) = aux_data_for_write;
563  * @vgpu: a vGPU
568 void intel_vgpu_init_i2c_edid(struct intel_vgpu *vgpu)
570 	struct intel_vgpu_i2c_edid *edid = &vgpu->display.i2c_edid;