Lines Matching refs:vgpu
38 static int get_edp_pipe(struct intel_vgpu *vgpu)
40 u32 data = vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP);
58 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
60 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
62 if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
65 if (!(vgpu_vreg(vgpu, _TRANS_DDI_FUNC_CTL_EDP) & TRANS_DDI_FUNC_ENABLE))
70 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
72 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
78 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
81 if (edp_pipe_is_enabled(vgpu) &&
82 get_edp_pipe(vgpu) == pipe)
170 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
172 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
180 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
185 vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
187 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
188 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
189 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
190 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
194 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
198 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
203 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
205 vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
209 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
214 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
217 vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
219 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
221 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
223 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
225 /* No hpd_invert set in vgpu vbt, need to clear invert mask */
226 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
227 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
229 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
230 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
232 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
234 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
235 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
237 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
238 vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
246 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
247 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
255 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
256 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
257 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
258 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
259 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
262 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
263 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
264 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
266 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
268 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
270 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
273 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
277 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
279 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
281 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
284 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
286 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
290 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
291 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
292 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
293 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
295 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
297 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
299 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
302 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
306 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
308 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
310 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
314 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
316 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
320 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
321 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
322 vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
323 vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
325 vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
327 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
329 vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
332 vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
336 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
338 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
340 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
344 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
346 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
353 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
361 vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
363 vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
376 vgpu_vreg_t(vgpu, DPLL_CTRL1) =
378 vgpu_vreg_t(vgpu, DPLL_CTRL1) |=
380 vgpu_vreg_t(vgpu, LCPLL1_CTL) =
382 vgpu_vreg_t(vgpu, DPLL_STATUS) = DPLL_LOCK(DPLL_ID_SKL_DPLL0);
389 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
390 vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
391 vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
392 vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
393 vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
396 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
397 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
399 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
401 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
403 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
404 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
407 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
412 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) &=
414 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_B)) |=
417 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |= DDI_BUF_CTL_ENABLE;
418 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &= ~DDI_BUF_IS_IDLE;
419 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTB_HOTPLUG_CPT;
422 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
423 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
425 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
427 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
429 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTC_HOTPLUG_CPT;
430 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
433 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
438 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) &=
440 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_C)) |=
443 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |= DDI_BUF_CTL_ENABLE;
444 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &= ~DDI_BUF_IS_IDLE;
445 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
448 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_D)) {
449 vgpu_vreg_t(vgpu, DPLL_CTRL2) &=
451 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
453 vgpu_vreg_t(vgpu, DPLL_CTRL2) |=
455 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
456 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
459 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
464 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) &=
466 vgpu_vreg_t(vgpu, PORT_CLK_SEL(PORT_D)) |=
469 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) |= DDI_BUF_CTL_ENABLE;
470 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_D)) &= ~DDI_BUF_IS_IDLE;
471 vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
478 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
479 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
482 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
484 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
487 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTA_HOTPLUG_SPT;
489 vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |= DDI_INIT_DISPLAY_DETECTED;
494 vgpu_vreg_t(vgpu, PCH_ADPA) &= ~ADPA_CRT_HOTPLUG_MONITOR_MASK;
498 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
499 vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
500 vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
501 vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
504 vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
507 static void clean_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num)
509 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
518 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
521 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
522 struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
547 emulate_monitor_status_change(vgpu);
564 struct intel_vgpu *vgpu;
569 for_each_active_vgpu(gvt, vgpu, id) {
571 if (pipe_is_enabled(vgpu, pipe)) {
590 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
592 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
593 struct intel_vgpu_irq *irq = &vgpu->irq;
607 if (!pipe_is_enabled(vgpu, pipe))
610 intel_vgpu_trigger_virtual_event(vgpu, event);
613 if (pipe_is_enabled(vgpu, pipe)) {
614 vgpu_vreg_t(vgpu, PIPE_FRMCOUNT_G4X(pipe))++;
615 intel_vgpu_trigger_virtual_event(vgpu, vblank_event[pipe]);
619 static void emulate_vblank(struct intel_vgpu *vgpu)
623 mutex_lock(&vgpu->vgpu_lock);
624 for_each_pipe(vgpu->gvt->gt->i915, pipe)
625 emulate_vblank_on_pipe(vgpu, pipe);
626 mutex_unlock(&vgpu->vgpu_lock);
638 struct intel_vgpu *vgpu;
642 for_each_active_vgpu(gvt, vgpu, id)
643 emulate_vblank(vgpu);
649 * @vgpu: a vGPU
655 void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
657 struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
665 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
667 vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
669 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
671 vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
673 vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
674 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
676 intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
678 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
680 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
683 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
686 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
688 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
690 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
692 intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
694 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
696 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
698 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
701 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
703 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
706 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
708 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
710 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
712 intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
714 if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
716 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
718 vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
721 vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
723 vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
726 vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
728 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
730 vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
732 intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
739 * @vgpu: a vGPU
744 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
746 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
752 clean_virtual_dp_monitor(vgpu, PORT_D);
754 clean_virtual_dp_monitor(vgpu, PORT_B);
759 * @vgpu: a vGPU
768 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
770 struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
772 intel_vgpu_init_i2c_edid(vgpu);
778 return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
781 return setup_virtual_dp_monitor(vgpu, PORT_B, GVT_DP_B,
787 * @vgpu: a vGPU
792 void intel_vgpu_reset_display(struct intel_vgpu *vgpu)
794 emulate_monitor_status_change(vgpu);