Lines Matching defs:temp
282 u32 dspcntr, pipeconf, dpll, temp;
326 temp = htotal_calculate(adjusted_mode);
327 REG_WRITE(htot_reg, temp);
343 temp = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
344 HDMI_WRITE(HDMI_HBLANK_A, ((adjusted_mode->crtc_hdisplay - 1) << 16) | temp);
383 u32 temp;
392 temp = REG_READ(DSPBCNTR);
393 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
394 REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);
402 temp = REG_READ(PIPEBCONF);
403 if ((temp & PIPEACONF_ENABLE) != 0) {
404 REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);
409 temp = REG_READ(PCH_PIPEBCONF);
410 if ((temp & PIPEACONF_ENABLE) != 0) {
411 REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);
419 temp = REG_READ(DPLL_CTRL);
420 if ((temp & DPLL_PWRDN) == 0) {
421 REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));
433 temp = REG_READ(DPLL_CTRL);
434 if ((temp & DPLL_PWRDN) != 0) {
435 REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));
436 temp = REG_READ(DPLL_CLK_ENABLE);
437 REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);
444 temp = REG_READ(PIPEBCONF);
445 if ((temp & PIPEACONF_ENABLE) == 0) {
446 REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);
451 temp = REG_READ(PCH_PIPEBCONF);
452 if ((temp & PIPEACONF_ENABLE) == 0) {
453 REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);
460 temp = REG_READ(DSPBCNTR);
461 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
462 REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);
499 u32 temp;
505 temp = 0x0;
507 temp = 0x99;
510 HDMI_WRITE(HDMI_VIDEO_REG, temp);
534 u32 temp;
536 temp = HDMI_READ(HDMI_HSR);
537 DRM_DEBUG_KMS("HDMI_HSR %x\n", temp);
539 if ((temp & HDMI_DETECT_HDP) != 0)