Lines Matching refs:psb
188 regs->psb.saveDSPARB = PSB_RVDC32(DSPARB);
189 regs->psb.saveDSPFW1 = PSB_RVDC32(DSPFW1);
190 regs->psb.saveDSPFW2 = PSB_RVDC32(DSPFW2);
191 regs->psb.saveDSPFW3 = PSB_RVDC32(DSPFW3);
192 regs->psb.saveDSPFW4 = PSB_RVDC32(DSPFW4);
193 regs->psb.saveDSPFW5 = PSB_RVDC32(DSPFW5);
194 regs->psb.saveDSPFW6 = PSB_RVDC32(DSPFW6);
195 regs->psb.saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
209 regs->psb.saveBCLRPAT_A = PSB_RVDC32(BCLRPAT_A);
218 regs->psb.saveDSPACURSOR_CTRL = PSB_RVDC32(CURACNTR);
219 regs->psb.saveDSPACURSOR_BASE = PSB_RVDC32(CURABASE);
220 regs->psb.saveDSPACURSOR_POS = PSB_RVDC32(CURAPOS);
230 regs->psb.savePERF_MODE = PSB_RVDC32(MRST_PERF_MODE);
233 regs->psb.savePP_CONTROL = PSB_RVDC32(PP_CONTROL);
234 regs->psb.savePFIT_PGM_RATIOS = PSB_RVDC32(PFIT_PGM_RATIOS);
235 regs->psb.savePFIT_AUTO_RATIOS = PSB_RVDC32(PFIT_AUTO_RATIOS);
238 regs->psb.saveLVDS = PSB_RVDC32(LVDS);
239 regs->psb.savePFIT_CONTROL = PSB_RVDC32(PFIT_CONTROL);
240 regs->psb.savePP_ON_DELAYS = PSB_RVDC32(LVDSPP_ON);
241 regs->psb.savePP_OFF_DELAYS = PSB_RVDC32(LVDSPP_OFF);
242 regs->psb.savePP_DIVISOR = PSB_RVDC32(PP_CYCLE);
245 regs->psb.saveOV_OVADD = PSB_RVDC32(OV_OVADD);
246 regs->psb.saveOV_OGAMC0 = PSB_RVDC32(OV_OGAMC0);
247 regs->psb.saveOV_OGAMC1 = PSB_RVDC32(OV_OGAMC1);
248 regs->psb.saveOV_OGAMC2 = PSB_RVDC32(OV_OGAMC2);
249 regs->psb.saveOV_OGAMC3 = PSB_RVDC32(OV_OGAMC3);
250 regs->psb.saveOV_OGAMC4 = PSB_RVDC32(OV_OGAMC4);
251 regs->psb.saveOV_OGAMC5 = PSB_RVDC32(OV_OGAMC5);
254 regs->psb.saveHISTOGRAM_INT_CONTROL_REG =
256 regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG =
258 regs->psb.savePWM_CONTROL_LOGIC = PSB_RVDC32(PWM_CONTROL_LOGIC);
302 PSB_WVDC32(regs->psb.saveDSPARB, DSPARB);
303 PSB_WVDC32(regs->psb.saveDSPFW1, DSPFW1);
304 PSB_WVDC32(regs->psb.saveDSPFW2, DSPFW2);
305 PSB_WVDC32(regs->psb.saveDSPFW3, DSPFW3);
306 PSB_WVDC32(regs->psb.saveDSPFW4, DSPFW4);
307 PSB_WVDC32(regs->psb.saveDSPFW5, DSPFW5);
308 PSB_WVDC32(regs->psb.saveDSPFW6, DSPFW6);
309 PSB_WVDC32(regs->psb.saveCHICKENBIT, DSPCHICKENBIT);
330 PSB_WVDC32(regs->psb.saveBCLRPAT_A, BCLRPAT_A);
333 PSB_WVDC32(regs->psb.savePERF_MODE, MRST_PERF_MODE);
349 PSB_WVDC32(regs->psb.saveDSPACURSOR_CTRL, CURACNTR);
350 PSB_WVDC32(regs->psb.saveDSPACURSOR_POS, CURAPOS);
351 PSB_WVDC32(regs->psb.saveDSPACURSOR_BASE, CURABASE);
362 PSB_WVDC32(regs->psb.saveLVDS, LVDS); /*port 61180h*/
363 PSB_WVDC32(regs->psb.savePFIT_CONTROL, PFIT_CONTROL);
364 PSB_WVDC32(regs->psb.savePFIT_PGM_RATIOS, PFIT_PGM_RATIOS);
365 PSB_WVDC32(regs->psb.savePFIT_AUTO_RATIOS, PFIT_AUTO_RATIOS);
367 PSB_WVDC32(regs->psb.savePP_ON_DELAYS, LVDSPP_ON);
368 PSB_WVDC32(regs->psb.savePP_OFF_DELAYS, LVDSPP_OFF);
369 PSB_WVDC32(regs->psb.savePP_DIVISOR, PP_CYCLE);
370 PSB_WVDC32(regs->psb.savePP_CONTROL, PP_CONTROL);
384 PSB_WVDC32(regs->psb.saveOV_OVADD, OV_OVADD);
385 PSB_WVDC32(regs->psb.saveOV_OGAMC0, OV_OGAMC0);
386 PSB_WVDC32(regs->psb.saveOV_OGAMC1, OV_OGAMC1);
387 PSB_WVDC32(regs->psb.saveOV_OGAMC2, OV_OGAMC2);
388 PSB_WVDC32(regs->psb.saveOV_OGAMC3, OV_OGAMC3);
389 PSB_WVDC32(regs->psb.saveOV_OGAMC4, OV_OGAMC4);
390 PSB_WVDC32(regs->psb.saveOV_OGAMC5, OV_OGAMC5);
393 PSB_WVDC32(regs->psb.saveHISTOGRAM_INT_CONTROL_REG,
395 PSB_WVDC32(regs->psb.saveHISTOGRAM_LOGIC_CONTROL_REG,
397 PSB_WVDC32(regs->psb.savePWM_CONTROL_LOGIC, PWM_CONTROL_LOGIC);