Lines Matching defs:clock
64 /* Reported 135MHz pixel clock is too high, needs adjustment */
2438 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal);
2662 mode->clock = le16_to_cpu(timing->pixel_clock) * 10;
2774 if (mode->clock > max_clock)
3194 * Detailed modes are limited to 10kHz pixel clock resolution,
3195 * so fix up anything that looks like CEA/HDMI mode, but the clock
3357 * Calculate the alternate clock for the CEA mode
3363 unsigned int clock = cea_mode->clock;
3366 return clock;
3374 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000);
3376 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001);
3378 return clock;
3422 if (!to_match->clock)
3433 clock1 = cea_mode.clock;
3436 if (abs(to_match->clock - clock1) > clock_tolerance &&
3437 abs(to_match->clock - clock2) > clock_tolerance)
3461 if (!to_match->clock)
3472 clock1 = cea_mode.clock;
3475 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) &&
3476 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2))
3510 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor
3525 if (!to_match->clock)
3536 clock1 = hdmi_mode->clock;
3539 if (abs(to_match->clock - clock1) > clock_tolerance &&
3540 abs(to_match->clock - clock2) > clock_tolerance)
3563 if (!to_match->clock)
3574 clock1 = hdmi_mode->clock;
3577 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) ||
3578 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) &&
3604 * with the alternate clock for certain CEA modes.
3626 clock1 = cea_mode->clock;
3631 if (mode->clock != clock1 && mode->clock != clock2)
3643 * sure to pick the "other" clock for the new mode.
3645 if (mode->clock != clock1)
3646 newmode->clock = clock1;
3648 newmode->clock = clock2;
4318 int clock1, clock2, clock;
4323 * allow 5kHz clock difference either way to account for
4324 * the 10kHz clock resolution limit of detailed timings.
4330 clock1 = cea_mode->clock;
4337 clock1 = cea_mode->clock;
4345 if (abs(mode->clock - clock1) < abs(mode->clock - clock2))
4346 clock = clock1;
4348 clock = clock2;
4350 if (mode->clock == clock)
4353 DRM_DEBUG("detailed mode matches %s VIC %d, adjusting clock %d -> %d\n",
4354 type, vic, mode->clock, clock);
4355 mode->clock = clock;
4898 /* max clock is 5000 KHz times block value */
4904 DRM_DEBUG_KMS("HF-VSDB: max TMDS clock %d kHz\n",
4993 "max TMDS clock %d kHz\n",
5232 mode->clock = pixel_clock * 10;